..
cxl_downstream.c
qom: Have class_init() take a const data argument
2025-04-25 17:00:41 +02:00
cxl_root_port.c
qom: Have class_init() take a const data argument
2025-04-25 17:00:41 +02:00
cxl_upstream.c
qom: Have class_init() take a const data argument
2025-04-25 17:00:41 +02:00
gen_pcie_root_port.c
qom: Have class_init() take a const data argument
2025-04-25 17:00:41 +02:00
i82801b11.c
qom: Have class_init() take a const data argument
2025-04-25 17:00:41 +02:00
ioh3420.c
qom: Have class_init() take a const data argument
2025-04-25 17:00:41 +02:00
Kconfig
hw/pci-bridge: Add a Kconfig switch for the normal PCI bridge
2024-10-21 13:25:12 +02:00
meson.build
hw/pci-bridge: Add a Kconfig switch for the normal PCI bridge
2024-10-21 13:25:12 +02:00
pci_bridge_dev.c
qom: Have class_init() take a const data argument
2025-04-25 17:00:41 +02:00
pci_expander_bridge.c
qom: Have class_init() take a const data argument
2025-04-25 17:00:41 +02:00
pci_expander_bridge_stubs.c
pci/pci_expander_bridge: For CXL HB delay the HB register memory region setup.
2022-06-09 19:32:49 -04:00
pcie_pci_bridge.c
qom: Have class_init() take a const data argument
2025-04-25 17:00:41 +02:00
pcie_root_port.c
qom: Have class_init() take a const data argument
2025-04-25 17:00:41 +02:00
simba.c
qom: Have class_init() take a const data argument
2025-04-25 17:00:41 +02:00
xio3130_downstream.c
qom: Have class_init() take a const data argument
2025-04-25 17:00:41 +02:00
xio3130_upstream.c
qom: Have class_init() take a const data argument
2025-04-25 17:00:41 +02:00