qemu/target
Philippe Mathieu-Daudé 0f81774dd1 target/riscv: Include missing 'accel/tcg/getpc.h' in csr.c
"accel/tcg/getpc.h" is pulled in indirectly. Include it
explicitly to avoid when refactoring unrelated headers:

  target/riscv/csr.c:2117:25: error: call to undeclared function 'GETPC' [-Wimplicit-function-declaration]
   2117 |     if ((val & RVC) && (GETPC() & ~3) != 0) {
        |                         ^

Note the TODO comment around GETPC() added upon introduction in
commit f18637cd61 ("RISC-V: Add misa runtime write support"):

 2099 static RISCVException write_misa(CPURISCVState *env, int csrno,
 2100                                  target_ulong val)
 2101 {
  ...
 2113     /*
 2114      * Suppress 'C' if next instruction is not aligned
 2115      * TODO: this should check next_pc
 2116      */
 2117     if ((val & RVC) && (GETPC() & ~3) != 0) {
 2118         val &= ~RVC;
 2119     }

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Mark Cave-Ayland <mark.caveayland@nutanix.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <20250424202412.91612-8-philmd@linaro.org>
2025-04-30 12:45:05 -07:00
..
alpha qom: Have class_init() take a const data argument 2025-04-25 17:00:41 +02:00
arm accel/tcg: Add CPUState arg to tb_invalidate_phys_range 2025-04-30 12:45:05 -07:00
avr qom: Have class_init() take a const data argument 2025-04-25 17:00:41 +02:00
hexagon target/hexagon: Include missing 'accel/tcg/getpc.h' 2025-04-25 17:09:58 +02:00
hppa target/hppa: Use tcg_gen_addcio_i64 2025-04-28 13:40:17 -07:00
i386 accel/tcg: Convert TARGET_HAS_PRECISE_SMC to TCGCPUOps.precise_smc 2025-04-30 12:45:05 -07:00
loongarch qom: Have class_init() take a const data argument 2025-04-25 17:00:41 +02:00
m68k qom: Have class_init() take a const data argument 2025-04-25 17:00:41 +02:00
microblaze target/microblaze: Use tcg_gen_addcio_i32 2025-04-28 13:40:17 -07:00
mips target/mips: Check CPU endianness at runtime using env_is_bigendian() 2025-04-25 17:09:58 +02:00
openrisc target/openrisc: Use tcg_gen_addcio_* for ADDC 2025-04-28 13:40:17 -07:00
ppc target/ppc: Use tcg_gen_addcio_tl for ADD and SUBF 2025-04-28 13:40:17 -07:00
riscv target/riscv: Include missing 'accel/tcg/getpc.h' in csr.c 2025-04-30 12:45:05 -07:00
rx qom: Have class_init() take a const data argument 2025-04-25 17:00:41 +02:00
s390x accel/tcg: Convert TARGET_HAS_PRECISE_SMC to TCGCPUOps.precise_smc 2025-04-30 12:45:05 -07:00
sh4 target/sh4: Use tcg_gen_addcio_i32 for addc 2025-04-28 13:40:17 -07:00
sparc target/sparc: Use tcg_gen_addcio_tl for gen_op_addcc_int 2025-04-28 13:40:17 -07:00
tricore target/tricore: Use tcg_gen_addcio_i32 for gen_addc_CC 2025-04-28 13:40:17 -07:00
xtensa target/xtensa: Evaluate TARGET_BIG_ENDIAN at compile time 2025-04-25 17:09:58 +02:00
Kconfig target/cris: Remove the deprecated CRIS target 2024-09-13 20:11:13 +02:00
meson.build target/cris: Remove the deprecated CRIS target 2024-09-13 20:11:13 +02:00