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0e5803dfbc
The Aspeed SoC has three different types of SMC (Static Memory Controller) controllers: the SMC (legacy), the FMC (the new one) and the SPI for the host PNOR. The FMC and the SPI models are now converging on the AST2500 SoC and the SMC, which was still available on the AST2400 SoC, was removed. The Aspeed SoC does not provide support for the legacy SMC controller. So, let's rename the 'smc' object to 'fmc' to clarify its nature. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Message-id: 1474977462-28032-2-git-send-email-clg@kaod.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
59 lines
1.4 KiB
C
59 lines
1.4 KiB
C
/*
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* ASPEED SoC family
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*
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* Andrew Jeffery <andrew@aj.id.au>
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*
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* Copyright 2016 IBM Corp.
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*
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* This code is licensed under the GPL version 2 or later. See
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* the COPYING file in the top-level directory.
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*/
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#ifndef ASPEED_SOC_H
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#define ASPEED_SOC_H
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#include "hw/arm/arm.h"
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#include "hw/intc/aspeed_vic.h"
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#include "hw/misc/aspeed_scu.h"
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#include "hw/misc/aspeed_sdmc.h"
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#include "hw/timer/aspeed_timer.h"
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#include "hw/i2c/aspeed_i2c.h"
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#include "hw/ssi/aspeed_smc.h"
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typedef struct AspeedSoCState {
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/*< private >*/
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DeviceState parent;
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/*< public >*/
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ARMCPU *cpu;
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MemoryRegion iomem;
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AspeedVICState vic;
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AspeedTimerCtrlState timerctrl;
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AspeedI2CState i2c;
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AspeedSCUState scu;
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AspeedSMCState fmc;
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AspeedSMCState spi;
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AspeedSDMCState sdmc;
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} AspeedSoCState;
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#define TYPE_ASPEED_SOC "aspeed-soc"
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#define ASPEED_SOC(obj) OBJECT_CHECK(AspeedSoCState, (obj), TYPE_ASPEED_SOC)
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typedef struct AspeedSoCInfo {
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const char *name;
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const char *cpu_model;
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uint32_t silicon_rev;
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hwaddr sdram_base;
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} AspeedSoCInfo;
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typedef struct AspeedSoCClass {
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DeviceClass parent_class;
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AspeedSoCInfo *info;
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} AspeedSoCClass;
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#define ASPEED_SOC_CLASS(klass) \
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OBJECT_CLASS_CHECK(AspeedSoCClass, (klass), TYPE_ASPEED_SOC)
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#define ASPEED_SOC_GET_CLASS(obj) \
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OBJECT_GET_CLASS(AspeedSoCClass, (obj), TYPE_ASPEED_SOC)
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#endif /* ASPEED_SOC_H */
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