Akihiko Odaki 0e350c1ada target/riscv: Remove misa_mxl validation ... It is initialized with a simple assignment and there is little room for error. In fact, the validation is even more complex. Signed-off-by: Akihiko Odaki <akihiko.odaki@daynix.com> Acked-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20240203-riscv-v11-1-a23f4848a628@daynix.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>		2024-02-09 20:43:14 +10:00
..
meson.build	target/riscv: introduce TCG AccelCPUClass	2023-10-12 11:55:21 +10:00
tcg-cpu.c	target/riscv: Remove misa_mxl validation	2024-02-09 20:43:14 +10:00
tcg-cpu.h	target/riscv: add riscv_cpu_accelerator_compatible()	2023-11-07 11:06:02 +10:00