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0cbad81f70
PAPR requires that the device tree's CPU nodes have several properties with information about the L1 cache. We already create two of these properties, but with incorrect names - "[id]cache-block-size" instead of "[id]-cache-block-size" (note the extra hyphen). We were also missing some of the required cache properties. This patch adds the [id]-cache-line-size properties (which have the same values as the block size properties in all current cases). We also add the [id]-cache-size properties. Adding the cache sizes requires some extra infrastructure in the general target-ppc code to (optionally) set the cache sizes for various CPUs. The CPU family descriptions in translate_init.c can set these sizes - this patch adds correct information for POWER7, I'm leaving other CPU types to people who have a physical example to verify against. In addition, for -cpu host we take the values advertised by the host (if available) and use those to override the information based on PVR. Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Alexander Graf <agraf@suse.de> |
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| .. | ||
| e500-ccsr.h | ||
| e500.c | ||
| e500.h | ||
| e500plat.c | ||
| mac.h | ||
| mac_newworld.c | ||
| mac_oldworld.c | ||
| Makefile.objs | ||
| mpc8544_guts.c | ||
| mpc8544ds.c | ||
| ppc.c | ||
| ppc4xx_devs.c | ||
| ppc4xx_pci.c | ||
| ppc405.h | ||
| ppc405_boards.c | ||
| ppc405_uc.c | ||
| ppc440_bamboo.c | ||
| ppc_booke.c | ||
| ppce500_spin.c | ||
| prep.c | ||
| spapr.c | ||
| spapr_events.c | ||
| spapr_hcall.c | ||
| spapr_iommu.c | ||
| spapr_pci.c | ||
| spapr_rtas.c | ||
| spapr_vio.c | ||
| virtex_ml507.c | ||
| xics.c | ||