mirror of
https://github.com/Motorhead1991/qemu.git
synced 2025-08-06 09:13:55 -06:00
0c575703e4
XIVE hcalls are all redirected to QEMU as none are on a fast path.
When necessary, QEMU invokes KVM through specific ioctls to perform
host operations. QEMU should have done the necessary checks before
calling KVM and, in case of failure, H_HARDWARE is simply returned.
H_INT_ESB is a special case that could have been handled under KVM
but the impact on performance was low when under QEMU. Here are some
figures :
kernel irqchip OFF ON
H_INT_ESB KVM QEMU
rtl8139 (LSI ) 1.19 1.24 1.23 Gbits/sec
virtio 31.80 42.30 -- Gbits/sec
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Message-Id: <20190513084245.25755-4-clg@kaod.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
78 lines
2.5 KiB
C
78 lines
2.5 KiB
C
/*
|
|
* QEMU PowerPC sPAPR XIVE interrupt controller model
|
|
*
|
|
* Copyright (c) 2017-2018, IBM Corporation.
|
|
*
|
|
* This code is licensed under the GPL version 2 or later. See the
|
|
* COPYING file in the top-level directory.
|
|
*/
|
|
|
|
#ifndef PPC_SPAPR_XIVE_H
|
|
#define PPC_SPAPR_XIVE_H
|
|
|
|
#include "hw/ppc/xive.h"
|
|
|
|
#define TYPE_SPAPR_XIVE "spapr-xive"
|
|
#define SPAPR_XIVE(obj) OBJECT_CHECK(SpaprXive, (obj), TYPE_SPAPR_XIVE)
|
|
|
|
typedef struct SpaprXive {
|
|
XiveRouter parent;
|
|
|
|
/* Internal interrupt source for IPIs and virtual devices */
|
|
XiveSource source;
|
|
hwaddr vc_base;
|
|
|
|
/* END ESB MMIOs */
|
|
XiveENDSource end_source;
|
|
hwaddr end_base;
|
|
|
|
/* DT */
|
|
gchar *nodename;
|
|
|
|
/* Routing table */
|
|
XiveEAS *eat;
|
|
uint32_t nr_irqs;
|
|
XiveEND *endt;
|
|
uint32_t nr_ends;
|
|
|
|
/* TIMA mapping address */
|
|
hwaddr tm_base;
|
|
MemoryRegion tm_mmio;
|
|
|
|
/* KVM support */
|
|
int fd;
|
|
void *tm_mmap;
|
|
} SpaprXive;
|
|
|
|
bool spapr_xive_irq_claim(SpaprXive *xive, uint32_t lisn, bool lsi);
|
|
bool spapr_xive_irq_free(SpaprXive *xive, uint32_t lisn);
|
|
void spapr_xive_pic_print_info(SpaprXive *xive, Monitor *mon);
|
|
|
|
void spapr_xive_hcall_init(SpaprMachineState *spapr);
|
|
void spapr_dt_xive(SpaprMachineState *spapr, uint32_t nr_servers, void *fdt,
|
|
uint32_t phandle);
|
|
void spapr_xive_set_tctx_os_cam(XiveTCTX *tctx);
|
|
void spapr_xive_mmio_set_enabled(SpaprXive *xive, bool enable);
|
|
void spapr_xive_map_mmio(SpaprXive *xive);
|
|
|
|
int spapr_xive_end_to_target(uint8_t end_blk, uint32_t end_idx,
|
|
uint32_t *out_server, uint8_t *out_prio);
|
|
|
|
/*
|
|
* KVM XIVE device helpers
|
|
*/
|
|
void kvmppc_xive_connect(SpaprXive *xive, Error **errp);
|
|
void kvmppc_xive_reset(SpaprXive *xive, Error **errp);
|
|
void kvmppc_xive_set_source_config(SpaprXive *xive, uint32_t lisn, XiveEAS *eas,
|
|
Error **errp);
|
|
void kvmppc_xive_sync_source(SpaprXive *xive, uint32_t lisn, Error **errp);
|
|
uint64_t kvmppc_xive_esb_rw(XiveSource *xsrc, int srcno, uint32_t offset,
|
|
uint64_t data, bool write);
|
|
void kvmppc_xive_set_queue_config(SpaprXive *xive, uint8_t end_blk,
|
|
uint32_t end_idx, XiveEND *end,
|
|
Error **errp);
|
|
void kvmppc_xive_get_queue_config(SpaprXive *xive, uint8_t end_blk,
|
|
uint32_t end_idx, XiveEND *end,
|
|
Error **errp);
|
|
|
|
#endif /* PPC_SPAPR_XIVE_H */
|