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-----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQEcBAABAgAGBQJb1yMkAAoJENSXKoln91plSrUIAIp8e63jdI/YX8gIp0iEVZmJ +QDAfgTRc3/zvIFYie4A4mEnEj6c8iwmrvINalxQ+tZDtNcMLU8zI+0bz2YxwgiT 1YbVrhNPJxqx65YOqwEAQ/vjlCC3iVtTP6s6eKpR5MZRBLUWrkuEub6gDWpKxrK0 lfSRXS8Bj2gAOzefxeLIcFhBcV/z8hlRe7wxGpSjmPcJ36G3Bv28nyV+LbfmCsTb QekIrEUtxlSqNJbb1apZHP1754mKURc43KoH6ZdXWXQWj2RedARltIfVxbprR0bK huYwwSSl1fD7ltvJW1gXGYKdRABUbvTMeRsheA7YwGXlIjeQLOAnkwc8ZwQkidU= =A7R3 -----END PGP SIGNATURE----- Merge remote-tracking branch 'remotes/amarkovic/tags/mips-queue-october-2018-part-4' into staging MIPS queue for October 2018, part 4 # gpg: Signature made Mon 29 Oct 2018 15:11:32 GMT # gpg: using RSA key D4972A8967F75A65 # gpg: Good signature from "Aleksandar Markovic <amarkovic@wavecomp.com>" # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 8526 FBF1 5DA3 811F 4A01 DD75 D497 2A89 67F7 5A65 * remotes/amarkovic/tags/mips-queue-october-2018-part-4: (27 commits) linux-user: Add prctl() PR_SET_FP_MODE and PR_GET_FP_MODE implementations linux-user: Determine the desired FPU mode from MIPS.abiflags linux-user: Read and set FP ABI value from MIPS abiflags linux-user: Extract MIPS abiflags from ELF file linux-user: Extend image_info struct with MIPS fp_abi and interp_fp_abi fields elf: Define MIPS_ABI_FP_UNKNOWN macro target/mips: Amend MXU ASE overview note target/mips: Move MXU_EN check one level higher target/mips: Add emulation of MXU instructions S32LDD and S32LDDR target/mips: Add emulation of MXU instructions Q8MUL and Q8MULSU target/mips: Add emulation of MXU instruction D16MAC target/mips: Add emulation of MXU instruction D16MUL target/mips: Add emulation of MXU instruction S8LDD target/mips: Move MUL, S32M2I, S32I2M handling out of main MXU switch target/mips: Add emulation of MXU instructions S32I2M and S32M2I target/mips: Add emulation of non-MXU MULL within MXU decoding engine target/mips: Add bit encoding for MXU operand getting pattern 'optn3' target/mips: Add bit encoding for MXU operand getting pattern 'optn2' target/mips: Add bit encoding for MXU execute add/sub pattern 'eptn2' target/mips: Add bit encoding for MXU accumulate add/sub 2-bit pattern 'aptn2' ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
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| block | ||
| chardev | ||
| crypto | ||
| disas | ||
| exec | ||
| fpu | ||
| hw | ||
| io | ||
| libdecnumber | ||
| migration | ||
| monitor | ||
| net | ||
| qapi | ||
| qemu | ||
| qom | ||
| scsi | ||
| standard-headers | ||
| sysemu | ||
| ui | ||
| elf.h | ||
| glib-compat.h | ||
| qemu-common.h | ||
| qemu-io.h | ||
| trace-tcg.h | ||