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https://github.com/Motorhead1991/qemu.git
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0b51fd0f99
Update TX and RX ring base address data type to uint64_t for 64 bits dram address DMA support. Both "Normal Priority Transmit Ring Base Address Register(0x20)" and "Receive Ring Base Address Register (0x24)" are used for saving the low part physical address of descriptor manager. Therefore, changes to set TX and RX descriptor manager address bits [31:0] in ftgmac100_read and ftgmac100_write functions. Incrementing the version of vmstate to 2. Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@redhat.com>
90 lines
1.7 KiB
C
90 lines
1.7 KiB
C
/*
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* Faraday FTGMAC100 Gigabit Ethernet
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*
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* Copyright (C) 2016-2017, IBM Corporation.
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*
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* This code is licensed under the GPL version 2 or later. See the
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* COPYING file in the top-level directory.
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*/
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#ifndef FTGMAC100_H
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#define FTGMAC100_H
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#include "qom/object.h"
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#define TYPE_FTGMAC100 "ftgmac100"
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OBJECT_DECLARE_SIMPLE_TYPE(FTGMAC100State, FTGMAC100)
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#define FTGMAC100_MEM_SIZE 0x1000
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#define FTGMAC100_REG_MEM_SIZE 0x100
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#include "hw/sysbus.h"
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#include "net/net.h"
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/*
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* Max frame size for the receiving buffer
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*/
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#define FTGMAC100_MAX_FRAME_SIZE 9220
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struct FTGMAC100State {
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/*< private >*/
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SysBusDevice parent_obj;
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/*< public >*/
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NICState *nic;
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NICConf conf;
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qemu_irq irq;
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MemoryRegion iomem_container;
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MemoryRegion iomem;
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uint8_t frame[FTGMAC100_MAX_FRAME_SIZE];
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uint32_t irq_state;
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uint32_t isr;
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uint32_t ier;
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uint32_t rx_enabled;
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uint32_t math[2];
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uint32_t rbsr;
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uint32_t itc;
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uint32_t aptcr;
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uint32_t dblac;
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uint32_t revr;
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uint32_t fear1;
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uint32_t tpafcr;
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uint32_t maccr;
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uint32_t phycr;
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uint32_t phydata;
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uint32_t fcr;
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uint64_t rx_ring;
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uint64_t rx_descriptor;
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uint64_t tx_ring;
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uint64_t tx_descriptor;
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uint32_t phy_status;
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uint32_t phy_control;
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uint32_t phy_advertise;
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uint32_t phy_int;
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uint32_t phy_int_mask;
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bool aspeed;
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uint32_t txdes0_edotr;
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uint32_t rxdes0_edorr;
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};
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#define TYPE_ASPEED_MII "aspeed-mmi"
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OBJECT_DECLARE_SIMPLE_TYPE(AspeedMiiState, ASPEED_MII)
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/*
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* AST2600 MII controller
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*/
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struct AspeedMiiState {
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/*< private >*/
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SysBusDevice parent_obj;
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FTGMAC100State *nic;
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MemoryRegion iomem;
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uint32_t phycr;
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uint32_t phydata;
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};
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#endif
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