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09c4e88759
The Ztso extension is already ratified, this adds it as a CPU property and adds various fences throughout the port in order to allow TSO targets to function on weaker hosts. We need no fences for AMOs as they're already SC, the places we need barriers are described. These fences are placed in the RISC-V backend rather than TCG as is planned for x86-on-arm64 because RISC-V allows heterogeneous (and likely soon dynamic) hart memory models. Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com> Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu> Message-ID: <20240207122256.902627-2-christoph.muellner@vrull.eu> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| .. | ||
| trans_privileged.c.inc | ||
| trans_rva.c.inc | ||
| trans_rvb.c.inc | ||
| trans_rvbf16.c.inc | ||
| trans_rvd.c.inc | ||
| trans_rvf.c.inc | ||
| trans_rvh.c.inc | ||
| trans_rvi.c.inc | ||
| trans_rvk.c.inc | ||
| trans_rvm.c.inc | ||
| trans_rvv.c.inc | ||
| trans_rvvk.c.inc | ||
| trans_rvzacas.c.inc | ||
| trans_rvzawrs.c.inc | ||
| trans_rvzce.c.inc | ||
| trans_rvzfa.c.inc | ||
| trans_rvzfh.c.inc | ||
| trans_rvzicbo.c.inc | ||
| trans_rvzicond.c.inc | ||
| trans_svinval.c.inc | ||
| trans_xthead.c.inc | ||
| trans_xventanacondops.c.inc | ||