Paolo Bonzini 243af0225a trace: switch position of headers to what Meson requires ... Meson doesn't enjoy the same flexibility we have with Make in choosing the include path. In particular the tracing headers are using $(build_root)/$(<D). In order to keep the include directives unchanged, the simplest solution is to generate headers with patterns like "trace/trace-audio.h" and place forwarding headers in the source tree such that for example "audio/trace.h" includes "trace/trace-audio.h". This patch is too ugly to be applied to the Makefiles now. It's only a way to separate the changes to the tracing header files from the Meson rewrite of the tracing logic. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>		2020-08-21 06:18:24 -04:00
..
boot.c	RISC-V: Support 64 bit start address	2020-07-13 17:25:37 -07:00
Kconfig	hw/char: Initial commit of Ibex UART	2020-06-19 08:24:07 -07:00
Makefile.objs	riscv: Initial commit of OpenTitan machine	2020-06-03 09:11:51 -07:00
opentitan.c	error: Eliminate error_propagate() with Coccinelle, part 1	2020-07-10 15:18:08 +02:00
riscv_hart.c	riscv_hart: Fix riscv_harts_realize() error API violations	2020-07-02 06:25:29 +02:00
riscv_htif.c	chardev: Use QEMUChrEvent enum in IOEventHandler typedef	2020-01-08 11:15:35 +01:00
sifive_clint.c	hw/riscv: Allow 64 bit access to SiFive CLINT	2020-07-02 09:19:32 -07:00
sifive_e.c	hw/riscv: sifive_e: Correct debug block size	2020-07-22 09:39:46 -07:00
sifive_e_prci.c	sysbus: Convert to sysbus_realize() etc. with Coccinelle	2020-06-15 22:05:28 +02:00
sifive_gpio.c	hw/riscv: sifive_gpio: Do not blindly trigger output IRQs	2020-06-19 08:25:27 -07:00
sifive_plic.c	riscv: plic: Add a couple of mising sifive_plic_update calls	2020-07-02 09:19:32 -07:00
sifive_test.c	sysbus: Convert to sysbus_realize() etc. with Coccinelle	2020-06-15 22:05:28 +02:00
sifive_u.c	hw: Mark nd_table[] misuse in realize methods FIXME	2020-07-21 08:41:15 +02:00
sifive_u_otp.c	qdev: set properties with device_class_set_props()	2020-01-24 20:59:15 +01:00
sifive_u_prci.c	riscv: sifive: Implement PRCI model for FU540	2019-09-17 08:42:47 -07:00
sifive_uart.c	chardev: Use QEMUChrEvent enum in IOEventHandler typedef	2020-01-08 11:15:35 +01:00
spike.c	hw/riscv: Modify MROM size to end at 0x10000	2020-07-13 17:25:37 -07:00
trace-events	SiFive RISC-V GPIO Device	2019-05-24 11:58:30 -07:00
trace.h	trace: switch position of headers to what Meson requires	2020-08-21 06:18:24 -04:00
virt.c	hw/riscv: Modify MROM size to end at 0x10000	2020-07-13 17:25:37 -07:00