Daniel Henrique Barboza bab2be1923 target/riscv/cpu.c: add 'ssstrict' to riscv, isa ... 'ssstrict' is a RVA23 profile-defined extension defined as follows: "No non-conforming extensions are present. Attempts to execute unimplemented opcodes or access unimplemented CSRs in the standard or reserved encoding spaces raises an illegal instruction exception that results in a contained trap to the supervisor-mode trap handler." In short, we need to throw an exception when accessing unimplemented CSRs or opcodes. We do that, so let's advertise it. Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Message-ID: <20250529202315.1684198-3-dbarboza@ventanamicro.com> Message-ID: <20250604174329.1147549-3-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>		2025-07-04 21:09:48 +10:00
..
aarch64/virt	qtest/bios-tables-test: Update blobs for its=off test on aarch64	2025-07-01 15:08:31 +01:00
riscv64/virt	target/riscv/cpu.c: add 'ssstrict' to riscv, isa	2025-07-04 21:09:48 +10:00
x86	tests: acpi: update expected blobs	2025-01-15 13:07:25 -05:00
disassemle-aml.sh	acpi/disassemle-aml.sh: fix up after dir reorg	2024-11-04 16:03:24 -05:00
rebuild-expected-aml.sh	tests/data/acpi/rebuild-expected-aml.sh: Add RISC-V	2024-07-03 18:14:07 -04:00