Taylor Simpson a5a8d98c85 Hexagon (target/hexagon) fix l2fetch instructions ... Y4_l2fetch == l2fetch(Rs32, Rt32) Y5_l2fetch == l2fetch(Rs32, Rtt32) The semantics for these instructions are present, but the encodings are missing. Note that these are treated as nops in qemu, so we add overrides. Test case added to tests/tcg/hexagon/misc.c Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <1622589584-22571-3-git-send-email-tsimpson@quicinc.com>		2021-06-29 11:32:50 -05:00
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allidefs.def	Hexagon (target/hexagon/imported) arch import	2021-02-18 07:48:22 -08:00
alu.idef	Hexagon (target/hexagon) add A4_addp_c/A4_subp_c	2021-05-01 08:31:43 -07:00
branch.idef	Hexagon (target/hexagon/imported) arch import	2021-02-18 07:48:22 -08:00
compare.idef	Hexagon (target/hexagon) cleanup ternary operators in semantics	2021-05-01 08:31:43 -07:00
encode.def	Hexagon (target/hexagon/imported) arch import	2021-02-18 07:48:22 -08:00
encode_pp.def	Hexagon (target/hexagon) fix l2fetch instructions	2021-06-29 11:32:50 -05:00
encode_subinsn.def	Hexagon (target/hexagon/imported) arch import	2021-02-18 07:48:22 -08:00
float.idef	Hexagon (target/hexagon) add F2_sfinvsqrta	2021-05-01 08:31:43 -07:00
iclass.def	Hexagon (target/hexagon) instruction classes	2021-02-18 07:48:22 -08:00
ldst.idef	Hexagon (target/hexagon) load into shifted register instructions	2021-05-01 16:06:11 -07:00
macros.def	Hexagon (target/hexagon) CABAC decode bin	2021-05-01 16:06:11 -07:00
mpy.idef	Hexagon (target/hexagon/imported) arch import	2021-02-18 07:48:22 -08:00
shift.idef	Hexagon (target/hexagon) CABAC decode bin	2021-05-01 16:06:11 -07:00
subinsns.idef	Hexagon (target/hexagon/imported) arch import	2021-02-18 07:48:22 -08:00
system.idef	Hexagon (target/hexagon/imported) arch import	2021-02-18 07:48:22 -08:00