Paolo Bonzini 034668c329 target/i386: correctly mask SSE4a bit indices in register operands ... SSE4a instructions EXTRQ and INSERTQ have two bit index operands, that can be immediates or taken from an XMM register. In both cases, the fields are 6-bit wide and the top two bits in the byte are ignored. translate.c is doing that correctly for the immediate case, but not for the XMM case, so fix it. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>		2022-09-19 15:16:00 +02:00
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alpha	accel/tcg: Add pc and host_pc params to gen_intermediate_code	2022-09-06 08:04:26 +01:00
arm	Convert m68k to semihosting/syscalls.h.	2022-09-17 10:30:34 -04:00
avr	accel/tcg: Add pc and host_pc params to gen_intermediate_code	2022-09-06 08:04:26 +01:00
cris	accel/tcg: Add pc and host_pc params to gen_intermediate_code	2022-09-06 08:04:26 +01:00
hexagon	accel/tcg: Add pc and host_pc params to gen_intermediate_code	2022-09-06 08:04:26 +01:00
hppa	accel/tcg: Add pc and host_pc params to gen_intermediate_code	2022-09-06 08:04:26 +01:00
i386	target/i386: correctly mask SSE4a bit indices in register operands	2022-09-19 15:16:00 +02:00
loongarch	accel/tcg: Add pc and host_pc params to gen_intermediate_code	2022-09-06 08:04:26 +01:00
m68k	target/m68k: Honour -semihosting-config userspace=on	2022-09-13 17:18:21 +01:00
microblaze	accel/tcg: Add pc and host_pc params to gen_intermediate_code	2022-09-06 08:04:26 +01:00
mips	target/mips: Honour -semihosting-config userspace=on	2022-09-13 17:18:21 +01:00
nios2	target/nios2: Honour -semihosting-config userspace=on	2022-09-13 17:18:21 +01:00
openrisc	accel/tcg: Add pc and host_pc params to gen_intermediate_code	2022-09-06 08:04:26 +01:00
ppc	accel/tcg: Add pc and host_pc params to gen_intermediate_code	2022-09-06 08:04:26 +01:00
riscv	target/riscv: Honour -semihosting-config userspace=on and enable=on	2022-09-13 17:18:21 +01:00
rx	accel/tcg: Add pc and host_pc params to gen_intermediate_code	2022-09-06 08:04:26 +01:00
s390x	target/s390x: Make translator stop before the end of a page	2022-09-06 08:04:26 +01:00
sh4	accel/tcg: Add pc and host_pc params to gen_intermediate_code	2022-09-06 08:04:26 +01:00
sparc	accel/tcg: Add pc and host_pc params to gen_intermediate_code	2022-09-06 08:04:26 +01:00
tricore	accel/tcg: Add pc and host_pc params to gen_intermediate_code	2022-09-06 08:04:26 +01:00
xtensa	target/xtensa: Honour -semihosting-config userspace=on	2022-09-13 17:18:21 +01:00
Kconfig	hw/loongarch: Add support loongson3 virt machine type.	2022-06-06 18:09:03 +00:00
meson.build	target/loongarch: Add target build suport	2022-06-06 18:09:03 +00:00