BALATON Zoltan d060b2789f hw/sd/sdhci: Set reset value of interrupt registers ... The interrupt enable registers are not reset to 0 on Freescale eSDHC but some bits are enabled on reset. At least some U-Boot versions seem to expect this and not initialise these registers before expecting interrupts. Use existing vendor property for Freescale eSDHC and set the reset value of the interrupt registers to match Freescale documentation. Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Message-ID: <20250210160329.DDA7F4E600E@zero.eik.bme.hu> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>		2025-03-11 20:00:16 +01:00
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allwinner-sdhost.h	hw: sd: allwinner-sdhost: Add sun50i-a64 SoC support	2023-06-06 10:19:33 +01:00
aspeed_sdhci.h	hw/sd/aspeed_sdhci: Add AST2700 Support	2024-12-11 07:25:53 +01:00
bcm2835_sdhost.h	Use OBJECT_DECLARE_SIMPLE_TYPE when possible	2020-09-18 14:12:32 -04:00
cadence_sdhci.h	hw/sd: Add Cadence SDHCI emulation	2020-09-09 15:54:18 -07:00
npcm7xx_sdhci.h	hw/arm/npcm7xx: Declare QOM macros using OBJECT_DECLARE_SIMPLE_TYPE()	2023-01-12 17:15:09 +00:00
sd.h	hw/sd: Remove unused 'enable' method from SDCardClass	2025-01-31 19:36:44 +01:00
sdhci.h	hw/sd/sdhci: Set reset value of interrupt registers	2025-03-11 20:00:16 +01:00