mirror of
https://github.com/Motorhead1991/qemu.git
synced 2025-08-25 11:01:52 -06:00
d060b2789f
The interrupt enable registers are not reset to 0 on Freescale eSDHC but some bits are enabled on reset. At least some U-Boot versions seem to expect this and not initialise these registers before expecting interrupts. Use existing vendor property for Freescale eSDHC and set the reset value of the interrupt registers to match Freescale documentation. Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Message-ID: <20250210160329.DDA7F4E600E@zero.eik.bme.hu> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> |
||
|---|---|---|
| .. | ||
| allwinner-sdhost.c | ||
| aspeed_sdhci.c | ||
| bcm2835_sdhost.c | ||
| cadence_sdhci.c | ||
| core.c | ||
| Kconfig | ||
| meson.build | ||
| npcm7xx_sdhci.c | ||
| omap_mmc.c | ||
| pl181.c | ||
| sd.c | ||
| sdhci-internal.h | ||
| sdhci-pci.c | ||
| sdhci.c | ||
| sdmmc-internal.h | ||
| ssi-sd.c | ||
| trace-events | ||
| trace.h | ||