mirror of
https://github.com/Motorhead1991/qemu.git
synced 2025-12-29 10:40:36 -07:00
a1f44e0c59
Add a regression test to verify that MEPC properly masks the lower bits when an address with mode bits is written to it, as required by the RISC-V Privileged Architecture specification. The test sets STVEC to an address with bit 0 set (vectored mode), triggers an illegal instruction exception, copies STVEC to MEPC in the trap handler, and verifies that MEPC masks bits [1:0] correctly for IALIGN=32. Without the fix, MEPC retains the mode bits (returns non-zero/FAIL). With the fix, MEPC clears bits [1:0] (returns 0/PASS). Signed-off-by: Charalampos Mitrodimas <charmitro@posteo.net> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Message-ID: <20250703182157.281320-3-charmitro@posteo.net> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
||
|---|---|---|
| .. | ||
| aarch64 | ||
| aarch64_be | ||
| alpha | ||
| arm | ||
| hexagon | ||
| hppa | ||
| i386 | ||
| loongarch64 | ||
| m68k | ||
| minilib | ||
| mips | ||
| multiarch | ||
| openrisc | ||
| plugins | ||
| ppc64 | ||
| ppc64le | ||
| riscv64 | ||
| s390x | ||
| sh4 | ||
| tricore | ||
| x86_64 | ||
| xtensa | ||
| xtensaeb | ||
| Makefile.target | ||
| README | ||
This directory contains various interesting guest binaries for regression testing the Tiny Code Generator doing system and user-mode emulation. The multiarch directory contains shared code for tests that can be built for all guest architectures. Architecture specific code can be found in their respective directories. System mode tests will be under the "system" subdirectories. GDB scripts for exercising the gdbstub on specific tests will be found under the "gdbstb" subdirectories. See the developer guide for more instructions on "make check-tcg"