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a2e3508ac0
This new header contains macros that define aarch64 registers.
In a subsequent patch, this will be replaced by a more exhaustive
version that will be generated from linux arch/arm64/tools/sysreg
file. Those macros are sufficient to migrate the storage of those
ID regs from named fields in isar struct to an array cell.
[CH: reworked to use different structures]
[CH: moved accessors from the patches first using them to here,
dropped interaction with writable registers, which will happen
later]
[CH: use DEF magic suggested by rth]
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Sebastian Ott <sebott@redhat.com>
Signed-off-by: Eric Auger <eric.auger@redhat.com>
Signed-off-by: Cornelia Huck <cohuck@redhat.com>
Message-id: 20250617153931.1330449-2-cohuck@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
42 lines
1.2 KiB
C
42 lines
1.2 KiB
C
/*
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* Definitions for Arm ID system registers
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*
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* SPDX-License-Identifier: GPL-2.0-or-later
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*/
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#ifndef ARM_CPU_SYSREGS_H
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#define ARM_CPU_SYSREGS_H
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/*
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* Following is similar to the coprocessor regs encodings, but with an argument
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* ordering that matches the ARM ARM. We also reuse the various CP_REG_ defines
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* that actually are the same as the equivalent KVM_REG_ values.
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*/
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#define ENCODE_ID_REG(op0, op1, crn, crm, op2) \
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(((op0) << CP_REG_ARM64_SYSREG_OP0_SHIFT) | \
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((op1) << CP_REG_ARM64_SYSREG_OP1_SHIFT) | \
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((crn) << CP_REG_ARM64_SYSREG_CRN_SHIFT) | \
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((crm) << CP_REG_ARM64_SYSREG_CRM_SHIFT) | \
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((op2) << CP_REG_ARM64_SYSREG_OP2_SHIFT))
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#define DEF(NAME, OP0, OP1, CRN, CRM, OP2) NAME##_IDX,
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typedef enum ARMIDRegisterIdx {
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#include "cpu-sysregs.h.inc"
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NUM_ID_IDX,
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} ARMIDRegisterIdx;
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#undef DEF
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#define DEF(NAME, OP0, OP1, CRN, CRM, OP2) \
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SYS_##NAME = ENCODE_ID_REG(OP0, OP1, CRN, CRM, OP2),
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typedef enum ARMSysRegs {
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#include "cpu-sysregs.h.inc"
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} ARMSysRegs;
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#undef DEF
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extern const uint32_t id_register_sysreg[NUM_ID_IDX];
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int get_sysreg_idx(ARMSysRegs sysreg);
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#endif /* ARM_CPU_SYSREGS_H */
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