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To support hpm events mmio writes, done via riscv_iommu_process_hpmevt_write(), we're also adding the 'hpm-counters' IOMMU property that are used to determine the amount of counters available in the IOMMU. Note that everything we did so far didn't change any IOMMU behavior because we're still not advertising HPM capability to software. This will be done in the next patch. Signed-off-by: Tomasz Jeznach <tjeznach@rivosinc.com> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20250224190826.1858473-9-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
33 lines
1.3 KiB
C
33 lines
1.3 KiB
C
/*
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* RISC-V IOMMU - Hardware Performance Monitor (HPM) helpers
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*
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* Copyright (C) 2022-2023 Rivos Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2 or later, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef HW_RISCV_IOMMU_HPM_H
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#define HW_RISCV_IOMMU_HPM_H
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#include "qom/object.h"
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#include "hw/riscv/riscv-iommu.h"
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uint64_t riscv_iommu_hpmcycle_read(RISCVIOMMUState *s);
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void riscv_iommu_hpm_incr_ctr(RISCVIOMMUState *s, RISCVIOMMUContext *ctx,
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unsigned event_id);
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void riscv_iommu_hpm_timer_cb(void *priv);
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void riscv_iommu_process_iocntinh_cy(RISCVIOMMUState *s, bool prev_cy_inh);
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void riscv_iommu_process_hpmcycle_write(RISCVIOMMUState *s);
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void riscv_iommu_process_hpmevt_write(RISCVIOMMUState *s, uint32_t evt_reg);
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#endif
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