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hw/pci-host/gpex: Allow more than 4 legacy IRQs

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Some boards such as vmapple don't do real legacy PCI IRQ swizzling.
Instead, they just keep allocating more board IRQ lines for each new
legacy IRQ. Let's support that mode by giving instantiators a new
"nr_irqs" property they can use to support more than 4 legacy IRQ lines.
In this mode, GPEX will export more IRQ lines, one for each device.

Signed-off-by: Alexander Graf <graf@amazon.com>
Signed-off-by: Phil Dennis-Jordan <phil@philjordan.eu>
Reviewed-by: Akihiko Odaki <akihiko.odaki@daynix.com>
Tested-by: Akihiko Odaki <akihiko.odaki@daynix.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-ID: <20241223221645.29911-9-phil@philjordan.eu>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
This commit is contained in:
Alexander Graf 2023-06-14 22:56:24 +00:00 • committed by Philippe Mathieu-Daudé
parent 7c89e226f8
commit ff871d0462
11 changed files with 61 additions and 37 deletions
Download patch file Download diff file Expand all files Collapse all files

2
hw/arm/sbsa-ref.c
View file

@ -673,7 +673,7 @@ static void create_pcie(SBSAMachineState *sms)
/* Map IO port space */ /* Map IO port space */
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, base_pio); sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, base_pio);
for (i = 0; i < GPEX_NUM_IRQS; i++) { for (i = 0; i < PCI_NUM_PINS; i++) {
sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, sysbus_connect_irq(SYS_BUS_DEVICE(dev), i,
qdev_get_gpio_in(sms->gic, irq + i)); qdev_get_gpio_in(sms->gic, irq + i));
gpex_set_irq_num(GPEX_HOST(dev), i, irq + i); gpex_set_irq_num(GPEX_HOST(dev), i, irq + i);

2
hw/arm/virt.c
View file

@ -1547,7 +1547,7 @@ static void create_pcie(VirtMachineState *vms)
/* Map IO port space */ /* Map IO port space */
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, base_pio); sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, base_pio);
for (i = 0; i < GPEX_NUM_IRQS; i++) { for (i = 0; i < PCI_NUM_PINS; i++) {
sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, sysbus_connect_irq(SYS_BUS_DEVICE(dev), i,
qdev_get_gpio_in(vms->gic, irq + i)); qdev_get_gpio_in(vms->gic, irq + i));
gpex_set_irq_num(GPEX_HOST(dev), i, irq + i); gpex_set_irq_num(GPEX_HOST(dev), i, irq + i);

2
hw/i386/microvm.c
View file

@ -139,7 +139,7 @@ static void create_gpex(MicrovmMachineState *mms)
mms->gpex.mmio64.base, mmio64_alias); mms->gpex.mmio64.base, mmio64_alias);
} }
for (i = 0; i < GPEX_NUM_IRQS; i++) { for (i = 0; i < PCI_NUM_PINS; i++) {
sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, sysbus_connect_irq(SYS_BUS_DEVICE(dev), i,
x86ms->gsi[mms->gpex.irq + i]); x86ms->gsi[mms->gpex.irq + i]);
} }

12
hw/loongarch/virt.c
View file

@ -452,7 +452,7 @@ static void fdt_add_pcie_irq_map_node(const LoongArchVirtMachineState *lvms,
{ {
int pin, dev; int pin, dev;
uint32_t irq_map_stride = 0; uint32_t irq_map_stride = 0;
uint32_t full_irq_map[GPEX_NUM_IRQS *GPEX_NUM_IRQS * 10] = {}; uint32_t full_irq_map[PCI_NUM_PINS * PCI_NUM_PINS * 10] = {};
uint32_t *irq_map = full_irq_map; uint32_t *irq_map = full_irq_map;
const MachineState *ms = MACHINE(lvms); const MachineState *ms = MACHINE(lvms);
@ -465,11 +465,11 @@ static void fdt_add_pcie_irq_map_node(const LoongArchVirtMachineState *lvms,
* to wrap to any number of devices. * to wrap to any number of devices.
*/ */
for (dev = 0; dev < GPEX_NUM_IRQS; dev++) { for (dev = 0; dev < PCI_NUM_PINS; dev++) {
int devfn = dev * 0x8; int devfn = dev * 0x8;
for (pin = 0; pin < GPEX_NUM_IRQS; pin++) { for (pin = 0; pin < PCI_NUM_PINS; pin++) {
int irq_nr = 16 + ((pin + PCI_SLOT(devfn)) % GPEX_NUM_IRQS); int irq_nr = 16 + ((pin + PCI_SLOT(devfn)) % PCI_NUM_PINS);
int i = 0; int i = 0;
/* Fill PCI address cells */ /* Fill PCI address cells */
@ -493,7 +493,7 @@ static void fdt_add_pcie_irq_map_node(const LoongArchVirtMachineState *lvms,
qemu_fdt_setprop(ms->fdt, nodename, "interrupt-map", full_irq_map, qemu_fdt_setprop(ms->fdt, nodename, "interrupt-map", full_irq_map,
GPEX_NUM_IRQS * GPEX_NUM_IRQS * PCI_NUM_PINS * PCI_NUM_PINS *
irq_map_stride * sizeof(uint32_t)); irq_map_stride * sizeof(uint32_t));
qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupt-map-mask", qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupt-map-mask",
0x1800, 0, 0, 0x7); 0x1800, 0, 0, 0x7);
@ -805,7 +805,7 @@ static void virt_devices_init(DeviceState *pch_pic,
memory_region_add_subregion(get_system_memory(), VIRT_PCI_IO_BASE, memory_region_add_subregion(get_system_memory(), VIRT_PCI_IO_BASE,
pio_alias); pio_alias);
for (i = 0; i < GPEX_NUM_IRQS; i++) { for (i = 0; i < PCI_NUM_PINS; i++) {
sysbus_connect_irq(d, i, sysbus_connect_irq(d, i,
qdev_get_gpio_in(pch_pic, 16 + i)); qdev_get_gpio_in(pch_pic, 16 + i));
gpex_set_irq_num(GPEX_HOST(gpex_dev), i, 16 + i); gpex_set_irq_num(GPEX_HOST(gpex_dev), i, 16 + i);

2
hw/mips/loongson3_virt.c
View file

@ -458,7 +458,7 @@ static inline void loongson3_virt_devices_init(MachineState *machine,
virt_memmap[VIRT_PCIE_PIO].base, s->pio_alias); virt_memmap[VIRT_PCIE_PIO].base, s->pio_alias);
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, virt_memmap[VIRT_PCIE_PIO].base); sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, virt_memmap[VIRT_PCIE_PIO].base);
for (i = 0; i < GPEX_NUM_IRQS; i++) { for (i = 0; i < PCI_NUM_PINS; i++) {
irq = qdev_get_gpio_in(pic, PCIE_IRQ_BASE + i); irq = qdev_get_gpio_in(pic, PCIE_IRQ_BASE + i);
sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, irq); sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, irq);
gpex_set_irq_num(GPEX_HOST(dev), i, PCIE_IRQ_BASE + i); gpex_set_irq_num(GPEX_HOST(dev), i, PCIE_IRQ_BASE + i);

12
hw/openrisc/virt.c
View file

@ -318,7 +318,7 @@ static void create_pcie_irq_map(void *fdt, char *nodename, int irq_base,
{ {
int pin, dev; int pin, dev;
uint32_t irq_map_stride = 0; uint32_t irq_map_stride = 0;
uint32_t full_irq_map[GPEX_NUM_IRQS * GPEX_NUM_IRQS * 6] = {}; uint32_t full_irq_map[PCI_NUM_PINS * PCI_NUM_PINS * 6] = {};
uint32_t *irq_map = full_irq_map; uint32_t *irq_map = full_irq_map;
/* /*
@ -330,11 +330,11 @@ static void create_pcie_irq_map(void *fdt, char *nodename, int irq_base,
* possible slot) seeing the interrupt-map-mask will allow the table * possible slot) seeing the interrupt-map-mask will allow the table
* to wrap to any number of devices. * to wrap to any number of devices.
*/ */
for (dev = 0; dev < GPEX_NUM_IRQS; dev++) { for (dev = 0; dev < PCI_NUM_PINS; dev++) {
int devfn = dev << 3; int devfn = dev << 3;
for (pin = 0; pin < GPEX_NUM_IRQS; pin++) { for (pin = 0; pin < PCI_NUM_PINS; pin++) {
int irq_nr = irq_base + ((pin + PCI_SLOT(devfn)) % GPEX_NUM_IRQS); int irq_nr = irq_base + ((pin + PCI_SLOT(devfn)) % PCI_NUM_PINS);
int i = 0; int i = 0;
/* Fill PCI address cells */ /* Fill PCI address cells */
@ -357,7 +357,7 @@ static void create_pcie_irq_map(void *fdt, char *nodename, int irq_base,
} }
qemu_fdt_setprop(fdt, nodename, "interrupt-map", full_irq_map, qemu_fdt_setprop(fdt, nodename, "interrupt-map", full_irq_map,
GPEX_NUM_IRQS * GPEX_NUM_IRQS * PCI_NUM_PINS * PCI_NUM_PINS *
irq_map_stride * sizeof(uint32_t)); irq_map_stride * sizeof(uint32_t));
qemu_fdt_setprop_cells(fdt, nodename, "interrupt-map-mask", qemu_fdt_setprop_cells(fdt, nodename, "interrupt-map-mask",
@ -409,7 +409,7 @@ static void openrisc_virt_pcie_init(OR1KVirtState *state,
memory_region_add_subregion(get_system_memory(), pio_base, alias); memory_region_add_subregion(get_system_memory(), pio_base, alias);
/* Connect IRQ lines. */ /* Connect IRQ lines. */
for (i = 0; i < GPEX_NUM_IRQS; i++) { for (i = 0; i < PCI_NUM_PINS; i++) {
pcie_irq = get_per_cpu_irq(cpus, num_cpus, irq_base + i); pcie_irq = get_per_cpu_irq(cpus, num_cpus, irq_base + i);
sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, pcie_irq); sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, pcie_irq);

43
hw/pci-host/gpex.c
View file

@ -32,6 +32,7 @@
#include "qemu/osdep.h" #include "qemu/osdep.h"
#include "qapi/error.h" #include "qapi/error.h"
#include "hw/irq.h" #include "hw/irq.h"
#include "hw/pci/pci_bus.h"
#include "hw/pci-host/gpex.h" #include "hw/pci-host/gpex.h"
#include "hw/qdev-properties.h" #include "hw/qdev-properties.h"
#include "migration/vmstate.h" #include "migration/vmstate.h"
@ -41,20 +42,25 @@
* GPEX host * GPEX host
*/ */
struct GPEXIrq {
qemu_irq irq;
int irq_num;
};
static void gpex_set_irq(void *opaque, int irq_num, int level) static void gpex_set_irq(void *opaque, int irq_num, int level)
{ {
GPEXHost *s = opaque; GPEXHost *s = opaque;
qemu_set_irq(s->irq[irq_num], level); qemu_set_irq(s->irq[irq_num].irq, level);
} }
int gpex_set_irq_num(GPEXHost *s, int index, int gsi) int gpex_set_irq_num(GPEXHost *s, int index, int gsi)
{ {
if (index >= GPEX_NUM_IRQS) { if (index >= s->num_irqs) {
return -EINVAL; return -EINVAL;
} }
s->irq_num[index] = gsi; s->irq[index].irq_num = gsi;
return 0; return 0;
} }
@ -62,7 +68,7 @@ static PCIINTxRoute gpex_route_intx_pin_to_irq(void *opaque, int pin)
{ {
PCIINTxRoute route; PCIINTxRoute route;
GPEXHost *s = opaque; GPEXHost *s = opaque;
int gsi = s->irq_num[pin]; int gsi = s->irq[pin].irq_num;
route.irq = gsi; route.irq = gsi;
if (gsi < 0) { if (gsi < 0) {
@ -74,6 +80,13 @@ static PCIINTxRoute gpex_route_intx_pin_to_irq(void *opaque, int pin)
return route; return route;
} }
static int gpex_swizzle_map_irq_fn(PCIDevice *pci_dev, int pin)
{
PCIBus *bus = pci_device_root_bus(pci_dev);
return (PCI_SLOT(pci_dev->devfn) + pin) % bus->nirq;
}
static void gpex_host_realize(DeviceState *dev, Error **errp) static void gpex_host_realize(DeviceState *dev, Error **errp)
{ {
PCIHostState *pci = PCI_HOST_BRIDGE(dev); PCIHostState *pci = PCI_HOST_BRIDGE(dev);
@ -82,6 +95,8 @@ static void gpex_host_realize(DeviceState *dev, Error **errp)
PCIExpressHost *pex = PCIE_HOST_BRIDGE(dev); PCIExpressHost *pex = PCIE_HOST_BRIDGE(dev);
int i; int i;
s->irq = g_malloc0_n(s->num_irqs, sizeof(*s->irq));
pcie_host_mmcfg_init(pex, PCIE_MMCFG_SIZE_MAX); pcie_host_mmcfg_init(pex, PCIE_MMCFG_SIZE_MAX);
sysbus_init_mmio(sbd, &pex->mmio); sysbus_init_mmio(sbd, &pex->mmio);
@ -128,19 +143,27 @@ static void gpex_host_realize(DeviceState *dev, Error **errp)
sysbus_init_mmio(sbd, &s->io_ioport); sysbus_init_mmio(sbd, &s->io_ioport);
} }
for (i = 0; i < GPEX_NUM_IRQS; i++) { for (i = 0; i < s->num_irqs; i++) {
sysbus_init_irq(sbd, &s->irq[i]); sysbus_init_irq(sbd, &s->irq[i].irq);
s->irq_num[i] = -1; s->irq[i].irq_num = -1;
} }
pci->bus = pci_register_root_bus(dev, "pcie.0", gpex_set_irq, pci->bus = pci_register_root_bus(dev, "pcie.0", gpex_set_irq,
pci_swizzle_map_irq_fn, s, &s->io_mmio, gpex_swizzle_map_irq_fn,
&s->io_ioport, 0, 4, TYPE_PCIE_BUS); s, &s->io_mmio, &s->io_ioport, 0,
s->num_irqs, TYPE_PCIE_BUS);
pci_bus_set_route_irq_fn(pci->bus, gpex_route_intx_pin_to_irq); pci_bus_set_route_irq_fn(pci->bus, gpex_route_intx_pin_to_irq);
qdev_realize(DEVICE(&s->gpex_root), BUS(pci->bus), &error_fatal); qdev_realize(DEVICE(&s->gpex_root), BUS(pci->bus), &error_fatal);
} }
static void gpex_host_unrealize(DeviceState *dev)
{
GPEXHost *s = GPEX_HOST(dev);
g_free(s->irq);
}
static const char *gpex_host_root_bus_path(PCIHostState *host_bridge, static const char *gpex_host_root_bus_path(PCIHostState *host_bridge,
PCIBus *rootbus) PCIBus *rootbus)
{ {
@ -166,6 +189,7 @@ static const Property gpex_host_properties[] = {
gpex_cfg.mmio64.base, 0), gpex_cfg.mmio64.base, 0),
DEFINE_PROP_SIZE(PCI_HOST_ABOVE_4G_MMIO_SIZE, GPEXHost, DEFINE_PROP_SIZE(PCI_HOST_ABOVE_4G_MMIO_SIZE, GPEXHost,
gpex_cfg.mmio64.size, 0), gpex_cfg.mmio64.size, 0),
DEFINE_PROP_UINT8("num-irqs", GPEXHost, num_irqs, PCI_NUM_PINS),
}; };
static void gpex_host_class_init(ObjectClass *klass, void *data) static void gpex_host_class_init(ObjectClass *klass, void *data)
@ -175,6 +199,7 @@ static void gpex_host_class_init(ObjectClass *klass, void *data)
hc->root_bus_path = gpex_host_root_bus_path; hc->root_bus_path = gpex_host_root_bus_path;
dc->realize = gpex_host_realize; dc->realize = gpex_host_realize;
dc->unrealize = gpex_host_unrealize;
set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
dc->fw_name = "pci"; dc->fw_name = "pci";
device_class_set_props(dc, gpex_host_properties); device_class_set_props(dc, gpex_host_properties);

12
hw/riscv/virt.c
View file

@ -179,7 +179,7 @@ static void create_pcie_irq_map(RISCVVirtState *s, void *fdt, char *nodename,
{ {
int pin, dev; int pin, dev;
uint32_t irq_map_stride = 0; uint32_t irq_map_stride = 0;
uint32_t full_irq_map[GPEX_NUM_IRQS * GPEX_NUM_IRQS * uint32_t full_irq_map[PCI_NUM_PINS * PCI_NUM_PINS *
FDT_MAX_INT_MAP_WIDTH] = {}; FDT_MAX_INT_MAP_WIDTH] = {};
uint32_t *irq_map = full_irq_map; uint32_t *irq_map = full_irq_map;
@ -191,11 +191,11 @@ static void create_pcie_irq_map(RISCVVirtState *s, void *fdt, char *nodename,
* possible slot) seeing the interrupt-map-mask will allow the table * possible slot) seeing the interrupt-map-mask will allow the table
* to wrap to any number of devices. * to wrap to any number of devices.
*/ */
for (dev = 0; dev < GPEX_NUM_IRQS; dev++) { for (dev = 0; dev < PCI_NUM_PINS; dev++) {
int devfn = dev * 0x8; int devfn = dev * 0x8;
for (pin = 0; pin < GPEX_NUM_IRQS; pin++) { for (pin = 0; pin < PCI_NUM_PINS; pin++) {
int irq_nr = PCIE_IRQ + ((pin + PCI_SLOT(devfn)) % GPEX_NUM_IRQS); int irq_nr = PCIE_IRQ + ((pin + PCI_SLOT(devfn)) % PCI_NUM_PINS);
int i = 0; int i = 0;
/* Fill PCI address cells */ /* Fill PCI address cells */
@ -221,7 +221,7 @@ static void create_pcie_irq_map(RISCVVirtState *s, void *fdt, char *nodename,
} }
qemu_fdt_setprop(fdt, nodename, "interrupt-map", full_irq_map, qemu_fdt_setprop(fdt, nodename, "interrupt-map", full_irq_map,
GPEX_NUM_IRQS * GPEX_NUM_IRQS * PCI_NUM_PINS * PCI_NUM_PINS *
irq_map_stride * sizeof(uint32_t)); irq_map_stride * sizeof(uint32_t));
qemu_fdt_setprop_cells(fdt, nodename, "interrupt-map-mask", qemu_fdt_setprop_cells(fdt, nodename, "interrupt-map-mask",
@ -1246,7 +1246,7 @@ static inline DeviceState *gpex_pcie_init(MemoryRegion *sys_mem,
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, pio_base); sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, pio_base);
for (i = 0; i < GPEX_NUM_IRQS; i++) { for (i = 0; i < PCI_NUM_PINS; i++) {
irq = qdev_get_gpio_in(irqchip, PCIE_IRQ + i); irq = qdev_get_gpio_in(irqchip, PCIE_IRQ + i);
sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, irq); sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, irq);

2
hw/xen/xen-pvh-common.c
View file

@ -169,7 +169,7 @@ static inline void xenpvh_gpex_init(XenPVHMachineState *s,
*/ */
assert(xpc->set_pci_intx_irq); assert(xpc->set_pci_intx_irq);
for (i = 0; i < GPEX_NUM_IRQS; i++) { for (i = 0; i < PCI_NUM_PINS; i++) {
qemu_irq irq = qemu_allocate_irq(xpc->set_pci_intx_irq, s, i); qemu_irq irq = qemu_allocate_irq(xpc->set_pci_intx_irq, s, i);
sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, irq); sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, irq);

2
hw/xtensa/virt.c
View file

@ -93,7 +93,7 @@ static void create_pcie(MachineState *ms, CPUXtensaState *env, int irq_base,
/* Connect IRQ lines. */ /* Connect IRQ lines. */
extints = xtensa_get_extints(env); extints = xtensa_get_extints(env);
for (i = 0; i < GPEX_NUM_IRQS; i++) { for (i = 0; i < PCI_NUM_PINS; i++) {
void *q = extints[irq_base + i]; void *q = extints[irq_base + i];
sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, q); sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, q);

7
include/hw/pci-host/gpex.h
View file

@ -32,8 +32,6 @@ OBJECT_DECLARE_SIMPLE_TYPE(GPEXHost, GPEX_HOST)
#define TYPE_GPEX_ROOT_DEVICE "gpex-root" #define TYPE_GPEX_ROOT_DEVICE "gpex-root"
OBJECT_DECLARE_SIMPLE_TYPE(GPEXRootState, GPEX_ROOT_DEVICE) OBJECT_DECLARE_SIMPLE_TYPE(GPEXRootState, GPEX_ROOT_DEVICE)
#define GPEX_NUM_IRQS 4
struct GPEXRootState { struct GPEXRootState {
/*< private >*/ /*< private >*/
PCIDevice parent_obj; PCIDevice parent_obj;
@ -49,6 +47,7 @@ struct GPEXConfig {
PCIBus *bus; PCIBus *bus;
}; };
typedef struct GPEXIrq GPEXIrq;
struct GPEXHost { struct GPEXHost {
/*< private >*/ /*< private >*/
PCIExpressHost parent_obj; PCIExpressHost parent_obj;
@ -60,8 +59,8 @@ struct GPEXHost {
MemoryRegion io_mmio; MemoryRegion io_mmio;
MemoryRegion io_ioport_window; MemoryRegion io_ioport_window;
MemoryRegion io_mmio_window; MemoryRegion io_mmio_window;
qemu_irq irq[GPEX_NUM_IRQS]; GPEXIrq *irq;
int irq_num[GPEX_NUM_IRQS]; uint8_t num_irqs;
bool allow_unmapped_accesses; bool allow_unmapped_accesses;