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target/arm: Implement SVE bitwise shift by wide elements (predicated)

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Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20180516223007.10256-13-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Richard Henderson 2018-05-18 17:48:08 +01:00 • committed by Peter Maydell
parent 27721dbb7a
commit fe7f8dfb2d
4 changed files with 86 additions and 0 deletions
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24
target/arm/translate-sve.c
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@ -497,6 +497,30 @@ static bool trans_ASRD(DisasContext *s, arg_rpri_esz *a, uint32_t insn)
}
}
/*
*** SVE Bitwise Shift - Predicated Group
*/
#define DO_ZPZW(NAME, name) \
static bool trans_##NAME##_zpzw(DisasContext *s, arg_rprr_esz *a, \
uint32_t insn) \
{ \
static gen_helper_gvec_4 * const fns[3] = { \
gen_helper_sve_##name##_zpzw_b, gen_helper_sve_##name##_zpzw_h, \
gen_helper_sve_##name##_zpzw_s, \
}; \
if (a->esz < 0 || a->esz >= 3) { \
return false; \
} \
return do_zpzz_ool(s, a, fns[a->esz]); \
}
DO_ZPZW(ASR, asr)
DO_ZPZW(LSR, lsr)
DO_ZPZW(LSL, lsl)
#undef DO_ZPZW
/*
*** SVE Predicate Logical Operations Group
*/