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igb: Add a VF reset handler

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Export the igb_vf_reset() helper routine from the PF model to let the
IGBVF model implement its own device reset.

Cc: Akihiko Odaki <akihiko.odaki@daynix.com>
Suggested-by: Sriram Yagnaraman <sriram.yagnaraman@est.tech>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Cédric Le Goater <clg@redhat.com>
Signed-off-by: Jason Wang <jasowang@redhat.com>
This commit is contained in:
Cédric Le Goater 2023-10-23 17:45:06 +02:00 • committed by Jason Wang
parent 69680740ea
commit fe73674af1
6 changed files with 25 additions and 2 deletions
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6
hw/net/igb.c
View file

@ -122,6 +122,12 @@ igb_mmio_write(void *opaque, hwaddr addr, uint64_t val, unsigned size)
igb_core_write(&s->core, addr, val, size); igb_core_write(&s->core, addr, val, size);
} }
void igb_vf_reset(void *opaque, uint16_t vfn)
{
IGBState *s = opaque;
igb_core_vf_reset(&s->core, vfn);
}
static bool static bool
igb_io_get_reg_index(IGBState *s, uint32_t *idx) igb_io_get_reg_index(IGBState *s, uint32_t *idx)
{ {

1
hw/net/igb_common.h
View file

@ -152,5 +152,6 @@ enum {
uint64_t igb_mmio_read(void *opaque, hwaddr addr, unsigned size); uint64_t igb_mmio_read(void *opaque, hwaddr addr, unsigned size);
void igb_mmio_write(void *opaque, hwaddr addr, uint64_t val, unsigned size); void igb_mmio_write(void *opaque, hwaddr addr, uint64_t val, unsigned size);
void igb_vf_reset(void *opaque, uint16_t vfn);
#endif #endif

6
hw/net/igb_core.c
View file

@ -2477,11 +2477,13 @@ static void igb_set_vfmailbox(IGBCore *core, int index, uint32_t val)
} }
} }
static void igb_vf_reset(IGBCore *core, uint16_t vfn) void igb_core_vf_reset(IGBCore *core, uint16_t vfn)
{ {
uint16_t qn0 = vfn; uint16_t qn0 = vfn;
uint16_t qn1 = vfn + IGB_NUM_VM_POOLS; uint16_t qn1 = vfn + IGB_NUM_VM_POOLS;
trace_igb_core_vf_reset(vfn);
/* disable Rx and Tx for the VF*/ /* disable Rx and Tx for the VF*/
core->mac[RXDCTL0 + (qn0 * 16)] &= ~E1000_RXDCTL_QUEUE_ENABLE; core->mac[RXDCTL0 + (qn0 * 16)] &= ~E1000_RXDCTL_QUEUE_ENABLE;
core->mac[RXDCTL0 + (qn1 * 16)] &= ~E1000_RXDCTL_QUEUE_ENABLE; core->mac[RXDCTL0 + (qn1 * 16)] &= ~E1000_RXDCTL_QUEUE_ENABLE;
@ -2560,7 +2562,7 @@ static void igb_set_vtctrl(IGBCore *core, int index, uint32_t val)
if (val & E1000_CTRL_RST) { if (val & E1000_CTRL_RST) {
vfn = (index - PVTCTRL0) / 0x40; vfn = (index - PVTCTRL0) / 0x40;
igb_vf_reset(core, vfn); igb_core_vf_reset(core, vfn);
} }
} }

3
hw/net/igb_core.h
View file

@ -130,6 +130,9 @@ igb_core_set_link_status(IGBCore *core);
void void
igb_core_pci_uninit(IGBCore *core); igb_core_pci_uninit(IGBCore *core);
void
igb_core_vf_reset(IGBCore *core, uint16_t vfn);
bool bool
igb_can_receive(IGBCore *core); igb_can_receive(IGBCore *core);

10
hw/net/igbvf.c
View file

@ -273,6 +273,13 @@ static void igbvf_pci_realize(PCIDevice *dev, Error **errp)
pcie_ari_init(dev, 0x150); pcie_ari_init(dev, 0x150);
} }
static void igbvf_qdev_reset_hold(Object *obj)
{
PCIDevice *vf = PCI_DEVICE(obj);
igb_vf_reset(pcie_sriov_get_pf(vf), pcie_sriov_vf_number(vf));
}
static void igbvf_pci_uninit(PCIDevice *dev) static void igbvf_pci_uninit(PCIDevice *dev)
{ {
IgbVfState *s = IGBVF(dev); IgbVfState *s = IGBVF(dev);
@ -287,6 +294,7 @@ static void igbvf_class_init(ObjectClass *class, void *data)
{ {
DeviceClass *dc = DEVICE_CLASS(class); DeviceClass *dc = DEVICE_CLASS(class);
PCIDeviceClass *c = PCI_DEVICE_CLASS(class); PCIDeviceClass *c = PCI_DEVICE_CLASS(class);
ResettableClass *rc = RESETTABLE_CLASS(class);
c->realize = igbvf_pci_realize; c->realize = igbvf_pci_realize;
c->exit = igbvf_pci_uninit; c->exit = igbvf_pci_uninit;
@ -295,6 +303,8 @@ static void igbvf_class_init(ObjectClass *class, void *data)
c->revision = 1; c->revision = 1;
c->class_id = PCI_CLASS_NETWORK_ETHERNET; c->class_id = PCI_CLASS_NETWORK_ETHERNET;
rc->phases.hold = igbvf_qdev_reset_hold;
dc->desc = "Intel 82576 Virtual Function"; dc->desc = "Intel 82576 Virtual Function";
dc->user_creatable = false; dc->user_creatable = false;

1
hw/net/trace-events
View file

@ -274,6 +274,7 @@ igb_core_mdic_read(uint32_t addr, uint32_t data) "MDIC READ: PHY[%u] = 0x%x"
igb_core_mdic_read_unhandled(uint32_t addr) "MDIC READ: PHY[%u] UNHANDLED" igb_core_mdic_read_unhandled(uint32_t addr) "MDIC READ: PHY[%u] UNHANDLED"
igb_core_mdic_write(uint32_t addr, uint32_t data) "MDIC WRITE: PHY[%u] = 0x%x" igb_core_mdic_write(uint32_t addr, uint32_t data) "MDIC WRITE: PHY[%u] = 0x%x"
igb_core_mdic_write_unhandled(uint32_t addr) "MDIC WRITE: PHY[%u] UNHANDLED" igb_core_mdic_write_unhandled(uint32_t addr) "MDIC WRITE: PHY[%u] UNHANDLED"
igb_core_vf_reset(uint16_t vfn) "VF%d"
igb_link_set_ext_params(bool asd_check, bool speed_select_bypass, bool pfrstd) "Set extended link params: ASD check: %d, Speed select bypass: %d, PF reset done: %d" igb_link_set_ext_params(bool asd_check, bool speed_select_bypass, bool pfrstd) "Set extended link params: ASD check: %d, Speed select bypass: %d, PF reset done: %d"