mirror of
https://github.com/Motorhead1991/qemu.git
synced 2026-03-14 14:56:05 -06:00
* Fix emulation of the LZRF instruction
* Fix "noexec" TCG test on s390x * Implement SHA-512 and random number generator instructions * Support for zPCI interpretation on s390x hosts * Removal of the "slirp" submodule -----BEGIN PGP SIGNATURE----- iQJFBAABCAAvFiEEJ7iIR+7gJQEY8+q5LtnXdP5wLbUFAmMx26URHHRodXRoQHJl ZGhhdC5jb20ACgkQLtnXdP5wLbUaOw/7Bu1ghYJyzjR8raXSzOP8KmyltKb0s0zd rFpagZCeBiNGHAL2IaKHc3vw+oFy/TTWhrFLt+imDo2swDIIAWCb/bY2/snKX4c8 feF0io7JTdNCWvS/9ng6qL/fGSNM6V2osYyN5fEm46DM7gC3GlAu5vP2TCVoIifw AXDANd6XngoCAFBdixGNi0yxAmiLCou/1S+lJ7hCbx1oICPPTrzuGBwyQ+IELJOD DUGFb+Dl4z+tv8OYRhdvoSTCz75IhsAXeny2+coffvW70BDSyhzIAtVeo2azVGvT aOVRJt+g7H/mJ0vH20M/7pakdwvHs3zciw5oHUJSsEW1HzsqNgl+AEEUzXivipaN LYp5//klqjjAu12hFQbzmbhD/vUw2+8mRgbJdKOz7rSrZ/K8f+jqIbbU5r8t1oyy BqLo2i0EVBfAomzbHMD/kmrumiSNIlfSDwScAoIKAO6P3oy/Sg2twMhPlFRWAnI0 46dQS1rLuU0nV4tMCAQoXxRxjQXytCOhaF9G+qe9ogLufHG+Uy+j3IeunyAUl9GR EcnRB0GFjWfZKeUsR9qev2pvgOZXeg4u+wpjGM7pmfpZw89nBqCj0UVAthXlSKoz ru3HcuBJTBtxwYkSCsPMEDCk/FhJN0D+N205qg+6SY28R57WjTPFLvZPRmhkH03E jN8rurLISAM= =FeSy -----END PGP SIGNATURE----- Merge tag 'pull-request-2022-09-26' of https://gitlab.com/thuth/qemu into staging * Fix emulation of the LZRF instruction * Fix "noexec" TCG test on s390x * Implement SHA-512 and random number generator instructions * Support for zPCI interpretation on s390x hosts * Removal of the "slirp" submodule # -----BEGIN PGP SIGNATURE----- # # iQJFBAABCAAvFiEEJ7iIR+7gJQEY8+q5LtnXdP5wLbUFAmMx26URHHRodXRoQHJl # ZGhhdC5jb20ACgkQLtnXdP5wLbUaOw/7Bu1ghYJyzjR8raXSzOP8KmyltKb0s0zd # rFpagZCeBiNGHAL2IaKHc3vw+oFy/TTWhrFLt+imDo2swDIIAWCb/bY2/snKX4c8 # feF0io7JTdNCWvS/9ng6qL/fGSNM6V2osYyN5fEm46DM7gC3GlAu5vP2TCVoIifw # AXDANd6XngoCAFBdixGNi0yxAmiLCou/1S+lJ7hCbx1oICPPTrzuGBwyQ+IELJOD # DUGFb+Dl4z+tv8OYRhdvoSTCz75IhsAXeny2+coffvW70BDSyhzIAtVeo2azVGvT # aOVRJt+g7H/mJ0vH20M/7pakdwvHs3zciw5oHUJSsEW1HzsqNgl+AEEUzXivipaN # LYp5//klqjjAu12hFQbzmbhD/vUw2+8mRgbJdKOz7rSrZ/K8f+jqIbbU5r8t1oyy # BqLo2i0EVBfAomzbHMD/kmrumiSNIlfSDwScAoIKAO6P3oy/Sg2twMhPlFRWAnI0 # 46dQS1rLuU0nV4tMCAQoXxRxjQXytCOhaF9G+qe9ogLufHG+Uy+j3IeunyAUl9GR # EcnRB0GFjWfZKeUsR9qev2pvgOZXeg4u+wpjGM7pmfpZw89nBqCj0UVAthXlSKoz # ru3HcuBJTBtxwYkSCsPMEDCk/FhJN0D+N205qg+6SY28R57WjTPFLvZPRmhkH03E # jN8rurLISAM= # =FeSy # -----END PGP SIGNATURE----- # gpg: Signature made Mon 26 Sep 2022 13:04:37 EDT # gpg: using RSA key 27B88847EEE0250118F3EAB92ED9D774FE702DB5 # gpg: issuer "thuth@redhat.com" # gpg: Good signature from "Thomas Huth <th.huth@gmx.de>" [full] # gpg: aka "Thomas Huth <thuth@redhat.com>" [full] # gpg: aka "Thomas Huth <huth@tuxfamily.org>" [full] # gpg: aka "Thomas Huth <th.huth@posteo.de>" [unknown] # Primary key fingerprint: 27B8 8847 EEE0 2501 18F3 EAB9 2ED9 D774 FE70 2DB5 * tag 'pull-request-2022-09-26' of https://gitlab.com/thuth/qemu: Remove the slirp submodule (i.e. compile only with an external libslirp) s390x/s390-virtio-ccw: add zpcii-disable machine property s390x/pci: reflect proper maxstbl for groups of interpreted devices s390x/pci: let intercept devices have separate PCI groups s390x/pci: enable adapter event notification for interpreted devices s390x/pci: don't fence interpreted devices without MSI-X s390x/pci: enable for load/store interpretation s390x/pci: add routine to get host function handle from CLP info Update linux headers to v6.0-rc4 configure: Add -Wno-gnu-variable-sized-type-not-at-end target/s390x: support PRNO_TRNG instruction target/s390x: support SHA-512 extensions linux-user/host/s390: Add vector instructions to host_signal_write() s390x/tcg: Fix opcode for lzrf Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
This commit is contained in:
Stefan Hajnoczi
commit
fe65642bba
53 changed files with 1287 additions and 270 deletions
|
|
@ -315,13 +315,16 @@ typedef struct ZpciFmb {
|
|||
QEMU_BUILD_BUG_MSG(offsetof(ZpciFmb, fmt0) != 48, "padding in ZpciFmb");
|
||||
|
||||
#define ZPCI_DEFAULT_FN_GRP 0xFF
|
||||
#define ZPCI_SIM_GRP_START 0xF0
|
||||
typedef struct S390PCIGroup {
|
||||
ClpRspQueryPciGrp zpci_group;
|
||||
int id;
|
||||
int host_id;
|
||||
QTAILQ_ENTRY(S390PCIGroup) link;
|
||||
} S390PCIGroup;
|
||||
S390PCIGroup *s390_group_create(int id);
|
||||
S390PCIGroup *s390_group_create(int id, int host_id);
|
||||
S390PCIGroup *s390_group_find(int id);
|
||||
S390PCIGroup *s390_group_find_host_sim(int host_id);
|
||||
|
||||
struct S390PCIBusDevice {
|
||||
DeviceState qdev;
|
||||
|
|
@ -350,6 +353,8 @@ struct S390PCIBusDevice {
|
|||
IndAddr *indicator;
|
||||
bool pci_unplug_request_processed;
|
||||
bool unplug_requested;
|
||||
bool interp;
|
||||
bool forwarding_assist;
|
||||
QTAILQ_ENTRY(S390PCIBusDevice) link;
|
||||
};
|
||||
|
||||
|
|
@ -368,6 +373,7 @@ struct S390pciState {
|
|||
QTAILQ_HEAD(, S390PCIBusDevice) zpci_devs;
|
||||
QTAILQ_HEAD(, S390PCIDMACount) zpci_dma_limit;
|
||||
QTAILQ_HEAD(, S390PCIGroup) zpci_groups;
|
||||
uint8_t next_sim_grp;
|
||||
};
|
||||
|
||||
S390pciState *s390_get_phb(void);
|
||||
|
|
|
|||
38
include/hw/s390x/s390-pci-kvm.h
Normal file
38
include/hw/s390x/s390-pci-kvm.h
Normal file
|
|
@ -0,0 +1,38 @@
|
|||
/*
|
||||
* s390 PCI KVM interfaces
|
||||
*
|
||||
* Copyright 2022 IBM Corp.
|
||||
* Author(s): Matthew Rosato <mjrosato@linux.ibm.com>
|
||||
*
|
||||
* This work is licensed under the terms of the GNU GPL, version 2 or (at
|
||||
* your option) any later version. See the COPYING file in the top-level
|
||||
* directory.
|
||||
*/
|
||||
|
||||
#ifndef HW_S390_PCI_KVM_H
|
||||
#define HW_S390_PCI_KVM_H
|
||||
|
||||
#include "hw/s390x/s390-pci-bus.h"
|
||||
#include "hw/s390x/s390-pci-inst.h"
|
||||
|
||||
#ifdef CONFIG_KVM
|
||||
bool s390_pci_kvm_interp_allowed(void);
|
||||
int s390_pci_kvm_aif_enable(S390PCIBusDevice *pbdev, ZpciFib *fib, bool assist);
|
||||
int s390_pci_kvm_aif_disable(S390PCIBusDevice *pbdev);
|
||||
#else
|
||||
static inline bool s390_pci_kvm_interp_allowed(void)
|
||||
{
|
||||
return false;
|
||||
}
|
||||
static inline int s390_pci_kvm_aif_enable(S390PCIBusDevice *pbdev, ZpciFib *fib,
|
||||
bool assist)
|
||||
{
|
||||
return -EINVAL;
|
||||
}
|
||||
static inline int s390_pci_kvm_aif_disable(S390PCIBusDevice *pbdev)
|
||||
{
|
||||
return -EINVAL;
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
|
@ -20,6 +20,7 @@ bool s390_pci_update_dma_avail(int fd, unsigned int *avail);
|
|||
S390PCIDMACount *s390_pci_start_dma_count(S390pciState *s,
|
||||
S390PCIBusDevice *pbdev);
|
||||
void s390_pci_end_dma_count(S390pciState *s, S390PCIDMACount *cnt);
|
||||
bool s390_pci_get_host_fh(S390PCIBusDevice *pbdev, uint32_t *fh);
|
||||
void s390_pci_get_clp_info(S390PCIBusDevice *pbdev);
|
||||
#else
|
||||
static inline bool s390_pci_update_dma_avail(int fd, unsigned int *avail)
|
||||
|
|
@ -33,6 +34,10 @@ static inline S390PCIDMACount *s390_pci_start_dma_count(S390pciState *s,
|
|||
}
|
||||
static inline void s390_pci_end_dma_count(S390pciState *s,
|
||||
S390PCIDMACount *cnt) { }
|
||||
static inline bool s390_pci_get_host_fh(S390PCIBusDevice *pbdev, uint32_t *fh)
|
||||
{
|
||||
return false;
|
||||
}
|
||||
static inline void s390_pci_get_clp_info(S390PCIBusDevice *pbdev) { }
|
||||
#endif
|
||||
|
||||
|
|
|
|||
|
|
@ -27,6 +27,7 @@ struct S390CcwMachineState {
|
|||
bool aes_key_wrap;
|
||||
bool dea_key_wrap;
|
||||
bool pv;
|
||||
bool zpcii_disable;
|
||||
uint8_t loadparm[8];
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -10,12 +10,13 @@
|
|||
#define SETUP_EFI 4
|
||||
#define SETUP_APPLE_PROPERTIES 5
|
||||
#define SETUP_JAILHOUSE 6
|
||||
#define SETUP_CC_BLOB 7
|
||||
#define SETUP_IMA 8
|
||||
#define SETUP_RNG_SEED 9
|
||||
#define SETUP_ENUM_MAX SETUP_RNG_SEED
|
||||
|
||||
#define SETUP_INDIRECT (1<<31)
|
||||
|
||||
/* SETUP_INDIRECT | max(SETUP_*) */
|
||||
#define SETUP_TYPE_MAX (SETUP_INDIRECT | SETUP_JAILHOUSE)
|
||||
#define SETUP_TYPE_MAX (SETUP_ENUM_MAX | SETUP_INDIRECT)
|
||||
|
||||
/* ram_size flags */
|
||||
#define RAMDISK_IMAGE_START_MASK 0x07FF
|
||||
|
|
|
|||
|
|
@ -558,7 +558,7 @@ extern "C" {
|
|||
*
|
||||
* The main surface is Y-tiled and is at plane index 0 whereas CCS is linear
|
||||
* and at index 1. The clear color is stored at index 2, and the pitch should
|
||||
* be ignored. The clear color structure is 256 bits. The first 128 bits
|
||||
* be 64 bytes aligned. The clear color structure is 256 bits. The first 128 bits
|
||||
* represents Raw Clear Color Red, Green, Blue and Alpha color each represented
|
||||
* by 32 bits. The raw clear color is consumed by the 3d engine and generates
|
||||
* the converted clear color of size 64 bits. The first 32 bits store the Lower
|
||||
|
|
@ -571,6 +571,53 @@ extern "C" {
|
|||
*/
|
||||
#define I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC fourcc_mod_code(INTEL, 8)
|
||||
|
||||
/*
|
||||
* Intel Tile 4 layout
|
||||
*
|
||||
* This is a tiled layout using 4KB tiles in a row-major layout. It has the same
|
||||
* shape as Tile Y at two granularities: 4KB (128B x 32) and 64B (16B x 4). It
|
||||
* only differs from Tile Y at the 256B granularity in between. At this
|
||||
* granularity, Tile Y has a shape of 16B x 32 rows, but this tiling has a shape
|
||||
* of 64B x 8 rows.
|
||||
*/
|
||||
#define I915_FORMAT_MOD_4_TILED fourcc_mod_code(INTEL, 9)
|
||||
|
||||
/*
|
||||
* Intel color control surfaces (CCS) for DG2 render compression.
|
||||
*
|
||||
* The main surface is Tile 4 and at plane index 0. The CCS data is stored
|
||||
* outside of the GEM object in a reserved memory area dedicated for the
|
||||
* storage of the CCS data for all RC/RC_CC/MC compressible GEM objects. The
|
||||
* main surface pitch is required to be a multiple of four Tile 4 widths.
|
||||
*/
|
||||
#define I915_FORMAT_MOD_4_TILED_DG2_RC_CCS fourcc_mod_code(INTEL, 10)
|
||||
|
||||
/*
|
||||
* Intel color control surfaces (CCS) for DG2 media compression.
|
||||
*
|
||||
* The main surface is Tile 4 and at plane index 0. For semi-planar formats
|
||||
* like NV12, the Y and UV planes are Tile 4 and are located at plane indices
|
||||
* 0 and 1, respectively. The CCS for all planes are stored outside of the
|
||||
* GEM object in a reserved memory area dedicated for the storage of the
|
||||
* CCS data for all RC/RC_CC/MC compressible GEM objects. The main surface
|
||||
* pitch is required to be a multiple of four Tile 4 widths.
|
||||
*/
|
||||
#define I915_FORMAT_MOD_4_TILED_DG2_MC_CCS fourcc_mod_code(INTEL, 11)
|
||||
|
||||
/*
|
||||
* Intel Color Control Surface with Clear Color (CCS) for DG2 render compression.
|
||||
*
|
||||
* The main surface is Tile 4 and at plane index 0. The CCS data is stored
|
||||
* outside of the GEM object in a reserved memory area dedicated for the
|
||||
* storage of the CCS data for all RC/RC_CC/MC compressible GEM objects. The
|
||||
* main surface pitch is required to be a multiple of four Tile 4 widths. The
|
||||
* clear color is stored at plane index 1 and the pitch should be 64 bytes
|
||||
* aligned. The format of the 256 bits of clear color data matches the one used
|
||||
* for the I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC modifier, see its description
|
||||
* for details.
|
||||
*/
|
||||
#define I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC fourcc_mod_code(INTEL, 12)
|
||||
|
||||
/*
|
||||
* Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks
|
||||
*
|
||||
|
|
@ -608,6 +655,28 @@ extern "C" {
|
|||
*/
|
||||
#define DRM_FORMAT_MOD_QCOM_COMPRESSED fourcc_mod_code(QCOM, 1)
|
||||
|
||||
/*
|
||||
* Qualcomm Tiled Format
|
||||
*
|
||||
* Similar to DRM_FORMAT_MOD_QCOM_COMPRESSED but not compressed.
|
||||
* Implementation may be platform and base-format specific.
|
||||
*
|
||||
* Each macrotile consists of m x n (mostly 4 x 4) tiles.
|
||||
* Pixel data pitch/stride is aligned with macrotile width.
|
||||
* Pixel data height is aligned with macrotile height.
|
||||
* Entire pixel data buffer is aligned with 4k(bytes).
|
||||
*/
|
||||
#define DRM_FORMAT_MOD_QCOM_TILED3 fourcc_mod_code(QCOM, 3)
|
||||
|
||||
/*
|
||||
* Qualcomm Alternate Tiled Format
|
||||
*
|
||||
* Alternate tiled format typically only used within GMEM.
|
||||
* Implementation may be platform and base-format specific.
|
||||
*/
|
||||
#define DRM_FORMAT_MOD_QCOM_TILED2 fourcc_mod_code(QCOM, 2)
|
||||
|
||||
|
||||
/* Vivante framebuffer modifiers */
|
||||
|
||||
/*
|
||||
|
|
@ -1293,6 +1362,7 @@ drm_fourcc_canonicalize_nvidia_format_mod(uint64_t modifier)
|
|||
#define AMD_FMT_MOD_TILE_VER_GFX9 1
|
||||
#define AMD_FMT_MOD_TILE_VER_GFX10 2
|
||||
#define AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS 3
|
||||
#define AMD_FMT_MOD_TILE_VER_GFX11 4
|
||||
|
||||
/*
|
||||
* 64K_S is the same for GFX9/GFX10/GFX10_RBPLUS and hence has GFX9 as canonical
|
||||
|
|
@ -1308,6 +1378,7 @@ drm_fourcc_canonicalize_nvidia_format_mod(uint64_t modifier)
|
|||
#define AMD_FMT_MOD_TILE_GFX9_64K_S_X 25
|
||||
#define AMD_FMT_MOD_TILE_GFX9_64K_D_X 26
|
||||
#define AMD_FMT_MOD_TILE_GFX9_64K_R_X 27
|
||||
#define AMD_FMT_MOD_TILE_GFX11_256K_R_X 31
|
||||
|
||||
#define AMD_FMT_MOD_DCC_BLOCK_64B 0
|
||||
#define AMD_FMT_MOD_DCC_BLOCK_128B 1
|
||||
|
|
|
|||
|
|
@ -257,7 +257,7 @@ struct ethtool_tunable {
|
|||
uint32_t id;
|
||||
uint32_t type_id;
|
||||
uint32_t len;
|
||||
void *data[0];
|
||||
void *data[];
|
||||
};
|
||||
|
||||
#define DOWNSHIFT_DEV_DEFAULT_COUNT 0xff
|
||||
|
|
@ -322,7 +322,7 @@ struct ethtool_regs {
|
|||
uint32_t cmd;
|
||||
uint32_t version;
|
||||
uint32_t len;
|
||||
uint8_t data[0];
|
||||
uint8_t data[];
|
||||
};
|
||||
|
||||
/**
|
||||
|
|
@ -348,7 +348,7 @@ struct ethtool_eeprom {
|
|||
uint32_t magic;
|
||||
uint32_t offset;
|
||||
uint32_t len;
|
||||
uint8_t data[0];
|
||||
uint8_t data[];
|
||||
};
|
||||
|
||||
/**
|
||||
|
|
@ -752,7 +752,7 @@ struct ethtool_gstrings {
|
|||
uint32_t cmd;
|
||||
uint32_t string_set;
|
||||
uint32_t len;
|
||||
uint8_t data[0];
|
||||
uint8_t data[];
|
||||
};
|
||||
|
||||
/**
|
||||
|
|
@ -777,7 +777,7 @@ struct ethtool_sset_info {
|
|||
uint32_t cmd;
|
||||
uint32_t reserved;
|
||||
uint64_t sset_mask;
|
||||
uint32_t data[0];
|
||||
uint32_t data[];
|
||||
};
|
||||
|
||||
/**
|
||||
|
|
@ -817,7 +817,7 @@ struct ethtool_test {
|
|||
uint32_t flags;
|
||||
uint32_t reserved;
|
||||
uint32_t len;
|
||||
uint64_t data[0];
|
||||
uint64_t data[];
|
||||
};
|
||||
|
||||
/**
|
||||
|
|
@ -834,7 +834,7 @@ struct ethtool_test {
|
|||
struct ethtool_stats {
|
||||
uint32_t cmd;
|
||||
uint32_t n_stats;
|
||||
uint64_t data[0];
|
||||
uint64_t data[];
|
||||
};
|
||||
|
||||
/**
|
||||
|
|
@ -851,7 +851,7 @@ struct ethtool_stats {
|
|||
struct ethtool_perm_addr {
|
||||
uint32_t cmd;
|
||||
uint32_t size;
|
||||
uint8_t data[0];
|
||||
uint8_t data[];
|
||||
};
|
||||
|
||||
/* boolean flags controlling per-interface behavior characteristics.
|
||||
|
|
@ -1160,7 +1160,7 @@ struct ethtool_rxnfc {
|
|||
struct ethtool_rxfh_indir {
|
||||
uint32_t cmd;
|
||||
uint32_t size;
|
||||
uint32_t ring_index[0];
|
||||
uint32_t ring_index[];
|
||||
};
|
||||
|
||||
/**
|
||||
|
|
@ -1201,7 +1201,7 @@ struct ethtool_rxfh {
|
|||
uint8_t hfunc;
|
||||
uint8_t rsvd8[3];
|
||||
uint32_t rsvd32;
|
||||
uint32_t rss_config[0];
|
||||
uint32_t rss_config[];
|
||||
};
|
||||
#define ETH_RXFH_CONTEXT_ALLOC 0xffffffff
|
||||
#define ETH_RXFH_INDIR_NO_CHANGE 0xffffffff
|
||||
|
|
@ -1286,7 +1286,7 @@ struct ethtool_dump {
|
|||
uint32_t version;
|
||||
uint32_t flag;
|
||||
uint32_t len;
|
||||
uint8_t data[0];
|
||||
uint8_t data[];
|
||||
};
|
||||
|
||||
#define ETH_FW_DUMP_DISABLE 0
|
||||
|
|
@ -1318,7 +1318,7 @@ struct ethtool_get_features_block {
|
|||
struct ethtool_gfeatures {
|
||||
uint32_t cmd;
|
||||
uint32_t size;
|
||||
struct ethtool_get_features_block features[0];
|
||||
struct ethtool_get_features_block features[];
|
||||
};
|
||||
|
||||
/**
|
||||
|
|
@ -1340,7 +1340,7 @@ struct ethtool_set_features_block {
|
|||
struct ethtool_sfeatures {
|
||||
uint32_t cmd;
|
||||
uint32_t size;
|
||||
struct ethtool_set_features_block features[0];
|
||||
struct ethtool_set_features_block features[];
|
||||
};
|
||||
|
||||
/**
|
||||
|
|
@ -1691,6 +1691,7 @@ enum ethtool_link_mode_bit_indices {
|
|||
ETHTOOL_LINK_MODE_400000baseCR4_Full_BIT = 89,
|
||||
ETHTOOL_LINK_MODE_100baseFX_Half_BIT = 90,
|
||||
ETHTOOL_LINK_MODE_100baseFX_Full_BIT = 91,
|
||||
ETHTOOL_LINK_MODE_10baseT1L_Full_BIT = 92,
|
||||
/* must be last entry */
|
||||
__ETHTOOL_LINK_MODE_MASK_NBITS
|
||||
};
|
||||
|
|
@ -2086,7 +2087,7 @@ struct ethtool_link_settings {
|
|||
uint8_t master_slave_state;
|
||||
uint8_t reserved1[1];
|
||||
uint32_t reserved[7];
|
||||
uint32_t link_mode_masks[0];
|
||||
uint32_t link_mode_masks[];
|
||||
/* layout of link_mode_masks fields:
|
||||
* uint32_t map_supported[link_mode_masks_nwords];
|
||||
* uint32_t map_advertising[link_mode_masks_nwords];
|
||||
|
|
|
|||
|
|
@ -75,10 +75,13 @@ struct input_id {
|
|||
* Note that input core does not clamp reported values to the
|
||||
* [minimum, maximum] limits, such task is left to userspace.
|
||||
*
|
||||
* The default resolution for main axes (ABS_X, ABS_Y, ABS_Z)
|
||||
* is reported in units per millimeter (units/mm), resolution
|
||||
* for rotational axes (ABS_RX, ABS_RY, ABS_RZ) is reported
|
||||
* in units per radian.
|
||||
* The default resolution for main axes (ABS_X, ABS_Y, ABS_Z,
|
||||
* ABS_MT_POSITION_X, ABS_MT_POSITION_Y) is reported in units
|
||||
* per millimeter (units/mm), resolution for rotational axes
|
||||
* (ABS_RX, ABS_RY, ABS_RZ) is reported in units per radian.
|
||||
* The resolution for the size axes (ABS_MT_TOUCH_MAJOR,
|
||||
* ABS_MT_TOUCH_MINOR, ABS_MT_WIDTH_MAJOR, ABS_MT_WIDTH_MINOR)
|
||||
* is reported in units per millimeter (units/mm).
|
||||
* When INPUT_PROP_ACCELEROMETER is set the resolution changes.
|
||||
* The main axes (ABS_X, ABS_Y, ABS_Z) are then reported in
|
||||
* units per g (units/g) and in units per degree per second
|
||||
|
|
@ -268,6 +271,7 @@ struct input_mask {
|
|||
#define BUS_RMI 0x1D
|
||||
#define BUS_CEC 0x1E
|
||||
#define BUS_INTEL_ISHTP 0x1F
|
||||
#define BUS_AMD_SFH 0x20
|
||||
|
||||
/*
|
||||
* MT_TOOL types
|
||||
|
|
|
|||
|
|
@ -616,6 +616,7 @@
|
|||
#define PCI_EXP_SLTCTL_PWR_OFF 0x0400 /* Power Off */
|
||||
#define PCI_EXP_SLTCTL_EIC 0x0800 /* Electromechanical Interlock Control */
|
||||
#define PCI_EXP_SLTCTL_DLLSCE 0x1000 /* Data Link Layer State Changed Enable */
|
||||
#define PCI_EXP_SLTCTL_ASPL_DISABLE 0x2000 /* Auto Slot Power Limit Disable */
|
||||
#define PCI_EXP_SLTCTL_IBPD_DISABLE 0x4000 /* In-band PD disable */
|
||||
#define PCI_EXP_SLTSTA 0x1a /* Slot Status */
|
||||
#define PCI_EXP_SLTSTA_ABP 0x0001 /* Attention Button Pressed */
|
||||
|
|
@ -736,7 +737,8 @@
|
|||
#define PCI_EXT_CAP_ID_DVSEC 0x23 /* Designated Vendor-Specific */
|
||||
#define PCI_EXT_CAP_ID_DLF 0x25 /* Data Link Feature */
|
||||
#define PCI_EXT_CAP_ID_PL_16GT 0x26 /* Physical Layer 16.0 GT/s */
|
||||
#define PCI_EXT_CAP_ID_MAX PCI_EXT_CAP_ID_PL_16GT
|
||||
#define PCI_EXT_CAP_ID_DOE 0x2E /* Data Object Exchange */
|
||||
#define PCI_EXT_CAP_ID_MAX PCI_EXT_CAP_ID_DOE
|
||||
|
||||
#define PCI_EXT_CAP_DSN_SIZEOF 12
|
||||
#define PCI_EXT_CAP_MCAST_ENDPOINT_SIZEOF 40
|
||||
|
|
@ -1102,4 +1104,30 @@
|
|||
#define PCI_PL_16GT_LE_CTRL_USP_TX_PRESET_MASK 0x000000F0
|
||||
#define PCI_PL_16GT_LE_CTRL_USP_TX_PRESET_SHIFT 4
|
||||
|
||||
/* Data Object Exchange */
|
||||
#define PCI_DOE_CAP 0x04 /* DOE Capabilities Register */
|
||||
#define PCI_DOE_CAP_INT_SUP 0x00000001 /* Interrupt Support */
|
||||
#define PCI_DOE_CAP_INT_MSG_NUM 0x00000ffe /* Interrupt Message Number */
|
||||
#define PCI_DOE_CTRL 0x08 /* DOE Control Register */
|
||||
#define PCI_DOE_CTRL_ABORT 0x00000001 /* DOE Abort */
|
||||
#define PCI_DOE_CTRL_INT_EN 0x00000002 /* DOE Interrupt Enable */
|
||||
#define PCI_DOE_CTRL_GO 0x80000000 /* DOE Go */
|
||||
#define PCI_DOE_STATUS 0x0c /* DOE Status Register */
|
||||
#define PCI_DOE_STATUS_BUSY 0x00000001 /* DOE Busy */
|
||||
#define PCI_DOE_STATUS_INT_STATUS 0x00000002 /* DOE Interrupt Status */
|
||||
#define PCI_DOE_STATUS_ERROR 0x00000004 /* DOE Error */
|
||||
#define PCI_DOE_STATUS_DATA_OBJECT_READY 0x80000000 /* Data Object Ready */
|
||||
#define PCI_DOE_WRITE 0x10 /* DOE Write Data Mailbox Register */
|
||||
#define PCI_DOE_READ 0x14 /* DOE Read Data Mailbox Register */
|
||||
|
||||
/* DOE Data Object - note not actually registers */
|
||||
#define PCI_DOE_DATA_OBJECT_HEADER_1_VID 0x0000ffff
|
||||
#define PCI_DOE_DATA_OBJECT_HEADER_1_TYPE 0x00ff0000
|
||||
#define PCI_DOE_DATA_OBJECT_HEADER_2_LENGTH 0x0003ffff
|
||||
|
||||
#define PCI_DOE_DATA_OBJECT_DISC_REQ_3_INDEX 0x000000ff
|
||||
#define PCI_DOE_DATA_OBJECT_DISC_RSP_3_VID 0x0000ffff
|
||||
#define PCI_DOE_DATA_OBJECT_DISC_RSP_3_PROTOCOL 0x00ff0000
|
||||
#define PCI_DOE_DATA_OBJECT_DISC_RSP_3_NEXT_INDEX 0xff000000
|
||||
|
||||
#endif /* LINUX_PCI_REGS_H */
|
||||
|
|
|
|||
|
|
@ -87,7 +87,7 @@ struct vhost_msg {
|
|||
|
||||
struct vhost_msg_v2 {
|
||||
uint32_t type;
|
||||
uint32_t reserved;
|
||||
uint32_t asid;
|
||||
union {
|
||||
struct vhost_iotlb_msg iotlb;
|
||||
uint8_t padding[64];
|
||||
|
|
@ -107,7 +107,7 @@ struct vhost_memory_region {
|
|||
struct vhost_memory {
|
||||
uint32_t nregions;
|
||||
uint32_t padding;
|
||||
struct vhost_memory_region regions[0];
|
||||
struct vhost_memory_region regions[];
|
||||
};
|
||||
|
||||
/* VHOST_SCSI specific definitions */
|
||||
|
|
@ -135,7 +135,7 @@ struct vhost_scsi_target {
|
|||
struct vhost_vdpa_config {
|
||||
uint32_t off;
|
||||
uint32_t len;
|
||||
uint8_t buf[0];
|
||||
uint8_t buf[];
|
||||
};
|
||||
|
||||
/* vhost vdpa IOVA range
|
||||
|
|
@ -153,4 +153,15 @@ struct vhost_vdpa_iova_range {
|
|||
/* vhost-net should add virtio_net_hdr for RX, and strip for TX packets. */
|
||||
#define VHOST_NET_F_VIRTIO_NET_HDR 27
|
||||
|
||||
/* Use message type V2 */
|
||||
#define VHOST_BACKEND_F_IOTLB_MSG_V2 0x1
|
||||
/* IOTLB can accept batching hints */
|
||||
#define VHOST_BACKEND_F_IOTLB_BATCH 0x2
|
||||
/* IOTLB can accept address space identifier through V2 type of IOTLB
|
||||
* message
|
||||
*/
|
||||
#define VHOST_BACKEND_F_IOTLB_ASID 0x3
|
||||
/* Device can be suspended */
|
||||
#define VHOST_BACKEND_F_SUSPEND 0x4
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -38,7 +38,7 @@ struct virtio_9p_config {
|
|||
/* length of the tag name */
|
||||
__virtio16 tag_len;
|
||||
/* non-NULL terminated tag name */
|
||||
uint8_t tag[0];
|
||||
uint8_t tag[];
|
||||
} QEMU_PACKED;
|
||||
|
||||
#endif /* _LINUX_VIRTIO_9P_H */
|
||||
|
|
|
|||
|
|
@ -52,7 +52,7 @@
|
|||
* rest are per-device feature bits.
|
||||
*/
|
||||
#define VIRTIO_TRANSPORT_F_START 28
|
||||
#define VIRTIO_TRANSPORT_F_END 38
|
||||
#define VIRTIO_TRANSPORT_F_END 41
|
||||
|
||||
#ifndef VIRTIO_CONFIG_NO_LEGACY
|
||||
/* Do we get callbacks when the ring is completely used, even if we've
|
||||
|
|
@ -96,4 +96,9 @@
|
|||
* Does the device support Single Root I/O Virtualization?
|
||||
*/
|
||||
#define VIRTIO_F_SR_IOV 37
|
||||
|
||||
/*
|
||||
* This feature indicates that the driver can reset a queue individually.
|
||||
*/
|
||||
#define VIRTIO_F_RING_RESET 40
|
||||
#endif /* _LINUX_VIRTIO_CONFIG_H */
|
||||
|
|
|
|||
|
|
@ -73,12 +73,12 @@
|
|||
* Virtio Transitional IDs
|
||||
*/
|
||||
|
||||
#define VIRTIO_TRANS_ID_NET 1000 /* transitional virtio net */
|
||||
#define VIRTIO_TRANS_ID_BLOCK 1001 /* transitional virtio block */
|
||||
#define VIRTIO_TRANS_ID_BALLOON 1002 /* transitional virtio balloon */
|
||||
#define VIRTIO_TRANS_ID_CONSOLE 1003 /* transitional virtio console */
|
||||
#define VIRTIO_TRANS_ID_SCSI 1004 /* transitional virtio SCSI */
|
||||
#define VIRTIO_TRANS_ID_RNG 1005 /* transitional virtio rng */
|
||||
#define VIRTIO_TRANS_ID_9P 1009 /* transitional virtio 9p console */
|
||||
#define VIRTIO_TRANS_ID_NET 0x1000 /* transitional virtio net */
|
||||
#define VIRTIO_TRANS_ID_BLOCK 0x1001 /* transitional virtio block */
|
||||
#define VIRTIO_TRANS_ID_BALLOON 0x1002 /* transitional virtio balloon */
|
||||
#define VIRTIO_TRANS_ID_CONSOLE 0x1003 /* transitional virtio console */
|
||||
#define VIRTIO_TRANS_ID_SCSI 0x1004 /* transitional virtio SCSI */
|
||||
#define VIRTIO_TRANS_ID_RNG 0x1005 /* transitional virtio rng */
|
||||
#define VIRTIO_TRANS_ID_9P 0x1009 /* transitional virtio 9p console */
|
||||
|
||||
#endif /* _LINUX_VIRTIO_IDS_H */
|
||||
|
|
|
|||
|
|
@ -56,7 +56,7 @@
|
|||
#define VIRTIO_NET_F_MQ 22 /* Device supports Receive Flow
|
||||
* Steering */
|
||||
#define VIRTIO_NET_F_CTRL_MAC_ADDR 23 /* Set MAC address */
|
||||
|
||||
#define VIRTIO_NET_F_NOTF_COAL 53 /* Device supports notifications coalescing */
|
||||
#define VIRTIO_NET_F_HASH_REPORT 57 /* Supports hash report */
|
||||
#define VIRTIO_NET_F_RSS 60 /* Supports RSS RX steering */
|
||||
#define VIRTIO_NET_F_RSC_EXT 61 /* extended coalescing info */
|
||||
|
|
@ -355,4 +355,36 @@ struct virtio_net_hash_config {
|
|||
#define VIRTIO_NET_CTRL_GUEST_OFFLOADS 5
|
||||
#define VIRTIO_NET_CTRL_GUEST_OFFLOADS_SET 0
|
||||
|
||||
/*
|
||||
* Control notifications coalescing.
|
||||
*
|
||||
* Request the device to change the notifications coalescing parameters.
|
||||
*
|
||||
* Available with the VIRTIO_NET_F_NOTF_COAL feature bit.
|
||||
*/
|
||||
#define VIRTIO_NET_CTRL_NOTF_COAL 6
|
||||
/*
|
||||
* Set the tx-usecs/tx-max-packets parameters.
|
||||
*/
|
||||
struct virtio_net_ctrl_coal_tx {
|
||||
/* Maximum number of packets to send before a TX notification */
|
||||
uint32_t tx_max_packets;
|
||||
/* Maximum number of usecs to delay a TX notification */
|
||||
uint32_t tx_usecs;
|
||||
};
|
||||
|
||||
#define VIRTIO_NET_CTRL_NOTF_COAL_TX_SET 0
|
||||
|
||||
/*
|
||||
* Set the rx-usecs/rx-max-packets parameters.
|
||||
*/
|
||||
struct virtio_net_ctrl_coal_rx {
|
||||
/* Maximum number of packets to receive before a RX notification */
|
||||
uint32_t rx_max_packets;
|
||||
/* Maximum number of usecs to delay a RX notification */
|
||||
uint32_t rx_usecs;
|
||||
};
|
||||
|
||||
#define VIRTIO_NET_CTRL_NOTF_COAL_RX_SET 1
|
||||
|
||||
#endif /* _LINUX_VIRTIO_NET_H */
|
||||
|
|
|
|||
|
|
@ -202,6 +202,8 @@ struct virtio_pci_cfg_cap {
|
|||
#define VIRTIO_PCI_COMMON_Q_AVAILHI 44
|
||||
#define VIRTIO_PCI_COMMON_Q_USEDLO 48
|
||||
#define VIRTIO_PCI_COMMON_Q_USEDHI 52
|
||||
#define VIRTIO_PCI_COMMON_Q_NDATA 56
|
||||
#define VIRTIO_PCI_COMMON_Q_RESET 58
|
||||
|
||||
#endif /* VIRTIO_PCI_NO_MODERN */
|
||||
|
||||
|
|
|
|||
|
|
@ -91,15 +91,21 @@
|
|||
#define VRING_USED_ALIGN_SIZE 4
|
||||
#define VRING_DESC_ALIGN_SIZE 16
|
||||
|
||||
/* Virtio ring descriptors: 16 bytes. These can chain together via "next". */
|
||||
/**
|
||||
* struct vring_desc - Virtio ring descriptors,
|
||||
* 16 bytes long. These can chain together via @next.
|
||||
*
|
||||
* @addr: buffer address (guest-physical)
|
||||
* @len: buffer length
|
||||
* @flags: descriptor flags
|
||||
* @next: index of the next descriptor in the chain,
|
||||
* if the VRING_DESC_F_NEXT flag is set. We chain unused
|
||||
* descriptors via this, too.
|
||||
*/
|
||||
struct vring_desc {
|
||||
/* Address (guest-physical). */
|
||||
__virtio64 addr;
|
||||
/* Length. */
|
||||
__virtio32 len;
|
||||
/* The flags as indicated above. */
|
||||
__virtio16 flags;
|
||||
/* We chain unused descriptors via this, too */
|
||||
__virtio16 next;
|
||||
};
|
||||
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue