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self-modifying code support
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@163 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
bellard
parent
727d01d4f6
commit
fd6ce8f660
3 changed files with 400 additions and 123 deletions
128
exec-i386.c
128
exec-i386.c
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@ -21,39 +21,10 @@
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#include "disas.h"
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//#define DEBUG_EXEC
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#define DEBUG_FLUSH
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//#define DEBUG_SIGNAL
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/* main execution loop */
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/* maximum total translate dcode allocated */
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#define CODE_GEN_BUFFER_SIZE (2048 * 1024)
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//#define CODE_GEN_BUFFER_SIZE (128 * 1024)
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#define CODE_GEN_MAX_SIZE 65536
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#define CODE_GEN_ALIGN 16 /* must be >= of the size of a icache line */
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/* threshold to flush the translated code buffer */
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#define CODE_GEN_BUFFER_MAX_SIZE (CODE_GEN_BUFFER_SIZE - CODE_GEN_MAX_SIZE)
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#define CODE_GEN_MAX_BLOCKS (CODE_GEN_BUFFER_SIZE / 64)
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#define CODE_GEN_HASH_BITS 15
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#define CODE_GEN_HASH_SIZE (1 << CODE_GEN_HASH_BITS)
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typedef struct TranslationBlock {
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unsigned long pc; /* simulated PC corresponding to this block (EIP + CS base) */
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unsigned long cs_base; /* CS base for this block */
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unsigned int flags; /* flags defining in which context the code was generated */
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uint8_t *tc_ptr; /* pointer to the translated code */
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struct TranslationBlock *hash_next; /* next matching block */
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} TranslationBlock;
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TranslationBlock tbs[CODE_GEN_MAX_BLOCKS];
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TranslationBlock *tb_hash[CODE_GEN_HASH_SIZE];
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int nb_tbs;
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uint8_t code_gen_buffer[CODE_GEN_BUFFER_SIZE];
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uint8_t *code_gen_ptr;
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/* thread support */
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#ifdef __powerpc__
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@ -195,70 +166,6 @@ void raise_exception(int exception_index)
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raise_exception_err(exception_index, 0);
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}
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void cpu_x86_tblocks_init(void)
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{
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if (!code_gen_ptr) {
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code_gen_ptr = code_gen_buffer;
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}
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}
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/* flush all the translation blocks */
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static void tb_flush(void)
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{
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int i;
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#ifdef DEBUG_FLUSH
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printf("gemu: flush code_size=%d nb_tbs=%d avg_tb_size=%d\n",
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code_gen_ptr - code_gen_buffer,
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nb_tbs,
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(code_gen_ptr - code_gen_buffer) / nb_tbs);
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#endif
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nb_tbs = 0;
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for(i = 0;i < CODE_GEN_HASH_SIZE; i++)
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tb_hash[i] = NULL;
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code_gen_ptr = code_gen_buffer;
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/* XXX: flush processor icache at this point */
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}
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/* find a translation block in the translation cache. If not found,
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return NULL and the pointer to the last element of the list in pptb */
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static inline TranslationBlock *tb_find(TranslationBlock ***pptb,
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unsigned long pc,
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unsigned long cs_base,
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unsigned int flags)
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{
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TranslationBlock **ptb, *tb;
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unsigned int h;
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h = pc & (CODE_GEN_HASH_SIZE - 1);
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ptb = &tb_hash[h];
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#if 0
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/* XXX: hack to handle 16 bit modyfing code */
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if (flags & (1 << GEN_FLAG_CODE32_SHIFT))
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#endif
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for(;;) {
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tb = *ptb;
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if (!tb)
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break;
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if (tb->pc == pc && tb->cs_base == cs_base && tb->flags == flags)
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return tb;
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ptb = &tb->hash_next;
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}
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*pptb = ptb;
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return NULL;
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}
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/* allocate a new translation block. flush the translation buffer if
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too many translation blocks or too much generated code */
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static inline TranslationBlock *tb_alloc(void)
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{
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TranslationBlock *tb;
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if (nb_tbs >= CODE_GEN_MAX_BLOCKS ||
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(code_gen_ptr - code_gen_buffer) >= CODE_GEN_BUFFER_MAX_SIZE)
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tb_flush();
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tb = &tbs[nb_tbs++];
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return tb;
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}
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int cpu_x86_exec(CPUX86State *env1)
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{
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int saved_T0, saved_T1, saved_A0;
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@ -287,7 +194,7 @@ int cpu_x86_exec(CPUX86State *env1)
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#ifdef reg_EDI
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int saved_EDI;
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#endif
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int code_gen_size, ret;
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int code_gen_size, ret, code_size;
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void (*gen_func)(void);
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TranslationBlock *tb, **ptb;
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uint8_t *tc_ptr, *cs_base, *pc;
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@ -390,15 +297,15 @@ int cpu_x86_exec(CPUX86State *env1)
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cpu_lock();
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tc_ptr = code_gen_ptr;
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ret = cpu_x86_gen_code(code_gen_ptr, CODE_GEN_MAX_SIZE,
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&code_gen_size, pc, cs_base, flags);
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&code_gen_size, pc, cs_base, flags,
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&code_size);
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/* if invalid instruction, signal it */
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if (ret != 0) {
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cpu_unlock();
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raise_exception(EXCP06_ILLOP);
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}
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tb = tb_alloc();
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tb = tb_alloc((unsigned long)pc, code_size);
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*ptb = tb;
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tb->pc = (unsigned long)pc;
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tb->cs_base = (unsigned long)cs_base;
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tb->flags = flags;
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tb->tc_ptr = tc_ptr;
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@ -493,15 +400,22 @@ void cpu_x86_load_seg(CPUX86State *s, int seg_reg, int selector)
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#include <sys/ucontext.h>
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/* 'pc' is the host PC at which the exception was raised. 'address' is
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the effective address of the memory exception */
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the effective address of the memory exception. 'is_write' is 1 if a
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write caused the exception and otherwise 0'. 'old_set' is the
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signal set which should be restored */
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static inline int handle_cpu_signal(unsigned long pc,
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unsigned long address,
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int is_write,
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sigset_t *old_set)
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{
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#ifdef DEBUG_SIGNAL
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printf("gemu: SIGSEGV pc=0x%08lx oldset=0x%08lx\n",
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pc, *(unsigned long *)old_set);
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#if defined(DEBUG_SIGNAL)
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printf("qemu: SIGSEGV pc=0x%08lx address=%08lx wr=%d oldset=0x%08lx\n",
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pc, address, is_write, *(unsigned long *)old_set);
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#endif
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if (is_write && page_unprotect(address)) {
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sigprocmask(SIG_SETMASK, old_set, NULL);
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return 1;
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}
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if (pc >= (unsigned long)code_gen_buffer &&
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pc < (unsigned long)code_gen_buffer + CODE_GEN_BUFFER_SIZE) {
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/* the PC is inside the translated code. It means that we have
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@ -512,8 +426,7 @@ static inline int handle_cpu_signal(unsigned long pc,
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/* XXX: need to compute virtual pc position by retranslating
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code. The rest of the CPU state should be correct. */
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env->cr2 = address;
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/* XXX: more precise exception code */
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raise_exception_err(EXCP0E_PAGE, 4);
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raise_exception_err(EXCP0E_PAGE, 4 | (is_write << 1));
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/* never comes here */
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return 1;
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} else {
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@ -531,11 +444,16 @@ int cpu_x86_signal_handler(int host_signum, struct siginfo *info,
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#ifndef REG_EIP
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/* for glibc 2.1 */
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#define REG_EIP EIP
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#define REG_EIP EIP
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#define REG_ERR ERR
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#define REG_TRAPNO TRAPNO
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#endif
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pc = uc->uc_mcontext.gregs[REG_EIP];
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pold_set = &uc->uc_sigmask;
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return handle_cpu_signal(pc, (unsigned long)info->si_addr, pold_set);
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return handle_cpu_signal(pc, (unsigned long)info->si_addr,
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uc->uc_mcontext.gregs[REG_TRAPNO] == 0xe ?
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(uc->uc_mcontext.gregs[REG_ERR] >> 1) & 1 : 0,
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pold_set);
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#else
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#warning No CPU specific signal handler: cannot handle target SIGSEGV events
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return 0;
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