motorhead/qemu
1
0
Fork 0
mirror of https://github.com/Motorhead1991/qemu.git synced 2025-08-05 08:43:55 -06:00
Code Issues Projects Releases Packages Wiki Activity Actions

target/riscv: Add instructions of the Zbc-extension

Browse source 
The following instructions are part of Zbc:
 - clmul
 - clmulh
 - clmulr

Note that these instructions were already defined in the pre-0.93 and
the 0.93 draft-B proposals, but had not been omitted in the earlier
addition of draft-B to QEmu.

Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210911140016.834071-10-philipp.tomsich@vrull.eu
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Philipp Tomsich 2021-09-11 16:00:09 +02:00 • committed by Alistair Francis
parent f36a4a89aa
commit fd4b81a304
4 changed files with 65 additions and 1 deletions
Download patch file Download diff file Expand all files Collapse all files

27
target/riscv/bitmanip_helper.c
View file

@ -3,6 +3,7 @@
*
* Copyright (c) 2020 Kito Cheng, kito.cheng@sifive.com
* Copyright (c) 2020 Frank Chang, frank.chang@sifive.com
* Copyright (c) 2021 Philipp Tomsich, philipp.tomsich@vrull.eu
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
@ -88,3 +89,29 @@ target_ulong HELPER(gorcw)(target_ulong rs1, target_ulong rs2)
{
return do_gorc(rs1, rs2, 32);
}
target_ulong HELPER(clmul)(target_ulong rs1, target_ulong rs2)
{
target_ulong result = 0;
for (int i = 0; i < TARGET_LONG_BITS; i++) {
if ((rs2 >> i) & 1) {
result ^= (rs1 << i);
}
}
return result;
}
target_ulong HELPER(clmulr)(target_ulong rs1, target_ulong rs2)
{
target_ulong result = 0;
for (int i = 0; i < TARGET_LONG_BITS; i++) {
if ((rs2 >> i) & 1) {
result ^= (rs1 >> (TARGET_LONG_BITS - i - 1));
}
}
return result;
}