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hw/arm/fsl-imx8mp: Add PCIe support

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Linux checks for the PLLs in the PHY to be locked, so implement a model
emulating that.

Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Message-id: 20250223114708.1780-9-shentey@gmail.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Bernhard Beschow 2025-02-23 12:46:58 +01:00 • committed by Peter Maydell
parent a81193c3e9
commit fd1deb5301
9 changed files with 176 additions and 0 deletions
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2
MAINTAINERS
View file

@ -827,8 +827,10 @@ S: Maintained
F: hw/arm/imx8mp-evk.c
F: hw/arm/fsl-imx8mp.c
F: hw/misc/imx8mp_*.c
F: hw/pci-host/fsl_imx8m_phy.c
F: include/hw/arm/fsl-imx8mp.h
F: include/hw/misc/imx8mp_*.h
F: include/hw/pci-host/fsl_imx8m_phy.h
F: docs/system/arm/imx8mp-evk.rst
MPS2 / MPS3

1
docs/system/arm/imx8mp-evk.rst
View file

@ -13,6 +13,7 @@ The ``imx8mp-evk`` machine implements the following devices:
* Generic Interrupt Controller (GICv3)
* 4 UARTs
* 3 USDHC Storage Controllers
* 1 Designware PCI Express Controller
* Secure Non-Volatile Storage (SNVS) including an RTC
* Clock Tree

3
hw/arm/Kconfig
View file

@ -595,10 +595,13 @@ config FSL_IMX7
config FSL_IMX8MP
bool
imply PCI_DEVICES
select ARM_GIC
select FSL_IMX8MP_ANALOG
select FSL_IMX8MP_CCM
select IMX
select PCI_EXPRESS_DESIGNWARE
select PCI_EXPRESS_FSL_IMX8M_PHY
select SDHCI
select UNIMP

30
hw/arm/fsl-imx8mp.c
View file

@ -212,6 +212,10 @@ static void fsl_imx8mp_init(Object *obj)
g_autofree char *name = g_strdup_printf("usdhc%d", i + 1);
object_initialize_child(obj, name, &s->usdhc[i], TYPE_IMX_USDHC);
}
object_initialize_child(obj, "pcie", &s->pcie, TYPE_DESIGNWARE_PCIE_HOST);
object_initialize_child(obj, "pcie_phy", &s->pcie_phy,
TYPE_FSL_IMX8M_PCIE_PHY);
}
static void fsl_imx8mp_realize(DeviceState *dev, Error **errp)
@ -380,6 +384,30 @@ static void fsl_imx8mp_realize(DeviceState *dev, Error **errp)
sysbus_mmio_map(SYS_BUS_DEVICE(&s->snvs), 0,
fsl_imx8mp_memmap[FSL_IMX8MP_SNVS_HP].addr);
/* PCIe */
if (!sysbus_realize(SYS_BUS_DEVICE(&s->pcie), errp)) {
return;
}
sysbus_mmio_map(SYS_BUS_DEVICE(&s->pcie), 0,
fsl_imx8mp_memmap[FSL_IMX8MP_PCIE1].addr);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->pcie), 0,
qdev_get_gpio_in(gicdev, FSL_IMX8MP_PCI_INTA_IRQ));
sysbus_connect_irq(SYS_BUS_DEVICE(&s->pcie), 1,
qdev_get_gpio_in(gicdev, FSL_IMX8MP_PCI_INTB_IRQ));
sysbus_connect_irq(SYS_BUS_DEVICE(&s->pcie), 2,
qdev_get_gpio_in(gicdev, FSL_IMX8MP_PCI_INTC_IRQ));
sysbus_connect_irq(SYS_BUS_DEVICE(&s->pcie), 3,
qdev_get_gpio_in(gicdev, FSL_IMX8MP_PCI_INTD_IRQ));
sysbus_connect_irq(SYS_BUS_DEVICE(&s->pcie), 4,
qdev_get_gpio_in(gicdev, FSL_IMX8MP_PCI_MSI_IRQ));
if (!sysbus_realize(SYS_BUS_DEVICE(&s->pcie_phy), errp)) {
return;
}
sysbus_mmio_map(SYS_BUS_DEVICE(&s->pcie_phy), 0,
fsl_imx8mp_memmap[FSL_IMX8MP_PCIE_PHY1].addr);
/* Unimplemented devices */
for (i = 0; i < ARRAY_SIZE(fsl_imx8mp_memmap); i++) {
switch (i) {
@ -387,6 +415,8 @@ static void fsl_imx8mp_realize(DeviceState *dev, Error **errp)
case FSL_IMX8MP_CCM:
case FSL_IMX8MP_GIC_DIST:
case FSL_IMX8MP_GIC_REDIST:
case FSL_IMX8MP_PCIE1:
case FSL_IMX8MP_PCIE_PHY1:
case FSL_IMX8MP_RAM:
case FSL_IMX8MP_SNVS_HP:
case FSL_IMX8MP_UART1 ... FSL_IMX8MP_UART4:

3
hw/pci-host/Kconfig
View file

@ -99,6 +99,9 @@ config ASTRO
bool
select PCI
config PCI_EXPRESS_FSL_IMX8M_PHY
bool
config GT64120
bool
select PCI

98
hw/pci-host/fsl_imx8m_phy.c Normal file
View file

@ -0,0 +1,98 @@
/*
* i.MX8 PCIe PHY emulation
*
* Copyright (c) 2025 Bernhard Beschow <shentey@gmail.com>
*
* SPDX-License-Identifier: GPL-2.0-or-later
*/
#include "qemu/osdep.h"
#include "hw/pci-host/fsl_imx8m_phy.h"
#include "hw/resettable.h"
#include "migration/vmstate.h"
#define CMN_REG075 0x1d4
#define ANA_PLL_LOCK_DONE BIT(1)
#define ANA_PLL_AFC_DONE BIT(0)
static uint64_t fsl_imx8m_pcie_phy_read(void *opaque, hwaddr offset,
unsigned size)
{
FslImx8mPciePhyState *s = opaque;
if (offset == CMN_REG075) {
return s->data[offset] | ANA_PLL_LOCK_DONE | ANA_PLL_AFC_DONE;
}
return s->data[offset];
}
static void fsl_imx8m_pcie_phy_write(void *opaque, hwaddr offset,
uint64_t value, unsigned size)
{
FslImx8mPciePhyState *s = opaque;
s->data[offset] = value;
}
static const MemoryRegionOps fsl_imx8m_pcie_phy_ops = {
.read = fsl_imx8m_pcie_phy_read,
.write = fsl_imx8m_pcie_phy_write,
.impl = {
.min_access_size = 1,
.max_access_size = 1,
},
.valid = {
.min_access_size = 1,
.max_access_size = 8,
},
.endianness = DEVICE_LITTLE_ENDIAN,
};
static void fsl_imx8m_pcie_phy_realize(DeviceState *dev, Error **errp)
{
FslImx8mPciePhyState *s = FSL_IMX8M_PCIE_PHY(dev);
memory_region_init_io(&s->iomem, OBJECT(s), &fsl_imx8m_pcie_phy_ops, s,
TYPE_FSL_IMX8M_PCIE_PHY, ARRAY_SIZE(s->data));
sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->iomem);
}
static void fsl_imx8m_pcie_phy_reset_hold(Object *obj, ResetType type)
{
FslImx8mPciePhyState *s = FSL_IMX8M_PCIE_PHY(obj);
memset(s->data, 0, sizeof(s->data));
}
static const VMStateDescription fsl_imx8m_pcie_phy_vmstate = {
.name = "fsl-imx8m-pcie-phy",
.version_id = 1,
.minimum_version_id = 1,
.fields = (const VMStateField[]) {
VMSTATE_UINT8_ARRAY(data, FslImx8mPciePhyState,
FSL_IMX8M_PCIE_PHY_DATA_SIZE),
VMSTATE_END_OF_LIST()
}
};
static void fsl_imx8m_pcie_phy_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
ResettableClass *rc = RESETTABLE_CLASS(klass);
dc->realize = fsl_imx8m_pcie_phy_realize;
dc->vmsd = &fsl_imx8m_pcie_phy_vmstate;
rc->phases.hold = fsl_imx8m_pcie_phy_reset_hold;
}
static const TypeInfo fsl_imx8m_pcie_phy_types[] = {
{
.name = TYPE_FSL_IMX8M_PCIE_PHY,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(FslImx8mPciePhyState),
.class_init = fsl_imx8m_pcie_phy_class_init,
}
};
DEFINE_TYPES(fsl_imx8m_pcie_phy_types)

1
hw/pci-host/meson.build
View file

@ -28,6 +28,7 @@ pci_ss.add(when: 'CONFIG_ARTICIA', if_true: files('articia.c'))
pci_ss.add(when: 'CONFIG_MV64361', if_true: files('mv64361.c'))
# ARM devices
pci_ss.add(when: 'CONFIG_PCI_EXPRESS_FSL_IMX8M_PHY', if_true: files('fsl_imx8m_phy.c'))
pci_ss.add(when: 'CONFIG_VERSATILE_PCI', if_true: files('versatile.c'))
# HPPA devices

10
include/hw/arm/fsl-imx8mp.h
View file

@ -15,6 +15,8 @@
#include "hw/misc/imx7_snvs.h"
#include "hw/misc/imx8mp_analog.h"
#include "hw/misc/imx8mp_ccm.h"
#include "hw/pci-host/designware.h"
#include "hw/pci-host/fsl_imx8m_phy.h"
#include "hw/sd/sdhci.h"
#include "qom/object.h"
#include "qemu/units.h"
@ -42,6 +44,8 @@ struct FslImx8mpState {
IMX7SNVSState snvs;
IMXSerialState uart[FSL_IMX8MP_NUM_UARTS];
SDHCIState usdhc[FSL_IMX8MP_NUM_USDHCS];
DesignwarePCIEHost pcie;
FslImx8mPciePhyState pcie_phy;
};
enum FslImx8mpMemoryRegions {
@ -197,6 +201,12 @@ enum FslImx8mpIrqs {
FSL_IMX8MP_UART4_IRQ = 29,
FSL_IMX8MP_UART5_IRQ = 30,
FSL_IMX8MP_UART6_IRQ = 16,
FSL_IMX8MP_PCI_INTA_IRQ = 126,
FSL_IMX8MP_PCI_INTB_IRQ = 125,
FSL_IMX8MP_PCI_INTC_IRQ = 124,
FSL_IMX8MP_PCI_INTD_IRQ = 123,
FSL_IMX8MP_PCI_MSI_IRQ = 140,
};
#endif /* FSL_IMX8MP_H */

28
include/hw/pci-host/fsl_imx8m_phy.h Normal file
View file

@ -0,0 +1,28 @@
/*
* i.MX8 PCIe PHY emulation
*
* Copyright (c) 2025 Bernhard Beschow <shentey@gmail.com>
*
* SPDX-License-Identifier: GPL-2.0-or-later
*/
#ifndef HW_PCIHOST_FSLIMX8MPCIEPHY_H
#define HW_PCIHOST_FSLIMX8MPCIEPHY_H
#include "hw/sysbus.h"
#include "qom/object.h"
#include "exec/memory.h"
#define TYPE_FSL_IMX8M_PCIE_PHY "fsl-imx8m-pcie-phy"
OBJECT_DECLARE_SIMPLE_TYPE(FslImx8mPciePhyState, FSL_IMX8M_PCIE_PHY)
#define FSL_IMX8M_PCIE_PHY_DATA_SIZE 0x800
struct FslImx8mPciePhyState {
SysBusDevice parent_obj;
MemoryRegion iomem;
uint8_t data[FSL_IMX8M_PCIE_PHY_DATA_SIZE];
};
#endif