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hw/arm/fsl-imx8mp: Add PCIe support
Linux checks for the PLLs in the PHY to be locked, so implement a model emulating that. Signed-off-by: Bernhard Beschow <shentey@gmail.com> Message-id: 20250223114708.1780-9-shentey@gmail.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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9 changed files with 176 additions and 0 deletions
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@ -212,6 +212,10 @@ static void fsl_imx8mp_init(Object *obj)
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g_autofree char *name = g_strdup_printf("usdhc%d", i + 1);
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object_initialize_child(obj, name, &s->usdhc[i], TYPE_IMX_USDHC);
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}
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object_initialize_child(obj, "pcie", &s->pcie, TYPE_DESIGNWARE_PCIE_HOST);
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object_initialize_child(obj, "pcie_phy", &s->pcie_phy,
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TYPE_FSL_IMX8M_PCIE_PHY);
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}
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static void fsl_imx8mp_realize(DeviceState *dev, Error **errp)
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@ -380,6 +384,30 @@ static void fsl_imx8mp_realize(DeviceState *dev, Error **errp)
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sysbus_mmio_map(SYS_BUS_DEVICE(&s->snvs), 0,
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fsl_imx8mp_memmap[FSL_IMX8MP_SNVS_HP].addr);
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/* PCIe */
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if (!sysbus_realize(SYS_BUS_DEVICE(&s->pcie), errp)) {
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return;
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}
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sysbus_mmio_map(SYS_BUS_DEVICE(&s->pcie), 0,
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fsl_imx8mp_memmap[FSL_IMX8MP_PCIE1].addr);
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sysbus_connect_irq(SYS_BUS_DEVICE(&s->pcie), 0,
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qdev_get_gpio_in(gicdev, FSL_IMX8MP_PCI_INTA_IRQ));
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sysbus_connect_irq(SYS_BUS_DEVICE(&s->pcie), 1,
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qdev_get_gpio_in(gicdev, FSL_IMX8MP_PCI_INTB_IRQ));
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sysbus_connect_irq(SYS_BUS_DEVICE(&s->pcie), 2,
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qdev_get_gpio_in(gicdev, FSL_IMX8MP_PCI_INTC_IRQ));
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sysbus_connect_irq(SYS_BUS_DEVICE(&s->pcie), 3,
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qdev_get_gpio_in(gicdev, FSL_IMX8MP_PCI_INTD_IRQ));
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sysbus_connect_irq(SYS_BUS_DEVICE(&s->pcie), 4,
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qdev_get_gpio_in(gicdev, FSL_IMX8MP_PCI_MSI_IRQ));
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if (!sysbus_realize(SYS_BUS_DEVICE(&s->pcie_phy), errp)) {
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return;
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}
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sysbus_mmio_map(SYS_BUS_DEVICE(&s->pcie_phy), 0,
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fsl_imx8mp_memmap[FSL_IMX8MP_PCIE_PHY1].addr);
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/* Unimplemented devices */
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for (i = 0; i < ARRAY_SIZE(fsl_imx8mp_memmap); i++) {
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switch (i) {
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@ -387,6 +415,8 @@ static void fsl_imx8mp_realize(DeviceState *dev, Error **errp)
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case FSL_IMX8MP_CCM:
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case FSL_IMX8MP_GIC_DIST:
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case FSL_IMX8MP_GIC_REDIST:
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case FSL_IMX8MP_PCIE1:
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case FSL_IMX8MP_PCIE_PHY1:
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case FSL_IMX8MP_RAM:
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case FSL_IMX8MP_SNVS_HP:
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case FSL_IMX8MP_UART1 ... FSL_IMX8MP_UART4:
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