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target/riscv: Add Zvknh ISA extension support
This commit adds support for the Zvknh vector-crypto extension, which consists of the following instructions: * vsha2ms.vv * vsha2c[hl].vv Translation functions are defined in `target/riscv/insn_trans/trans_rvvk.c.inc` and helpers are defined in `target/riscv/vcrypto_helper.c`. Co-authored-by: Nazar Kazakov <nazar.kazakov@codethink.co.uk> Co-authored-by: Lawrence Hunter <lawrence.hunter@codethink.co.uk> [max.chou@sifive.com: Replaced vstart checking by TCG op] Signed-off-by: Nazar Kazakov <nazar.kazakov@codethink.co.uk> Signed-off-by: Lawrence Hunter <lawrence.hunter@codethink.co.uk> Signed-off-by: Kiran Ostrolenk <kiran.ostrolenk@codethink.co.uk> Signed-off-by: Max Chou <max.chou@sifive.com> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> [max.chou@sifive.com: Exposed x-zvknha & x-zvknhb properties] [max.chou@sifive.com: Replaced SEW selection to happened during translation] Message-ID: <20230711165917.2629866-11-max.chou@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Kiran Ostrolenk
Alistair Francis
parent
e972bf22f6
commit
fcf1943376
6 changed files with 390 additions and 3 deletions
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@ -397,3 +397,241 @@ void HELPER(vaeskf2_vi)(void *vd_vptr, void *vs2_vptr, uint32_t uimm,
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/* set tail elements to 1s */
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vext_set_elems_1s(vd, vta, vl * 4, total_elems * 4);
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}
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static inline uint32_t sig0_sha256(uint32_t x)
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{
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return ror32(x, 7) ^ ror32(x, 18) ^ (x >> 3);
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}
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static inline uint32_t sig1_sha256(uint32_t x)
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{
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return ror32(x, 17) ^ ror32(x, 19) ^ (x >> 10);
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}
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static inline uint64_t sig0_sha512(uint64_t x)
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{
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return ror64(x, 1) ^ ror64(x, 8) ^ (x >> 7);
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}
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static inline uint64_t sig1_sha512(uint64_t x)
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{
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return ror64(x, 19) ^ ror64(x, 61) ^ (x >> 6);
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}
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static inline void vsha2ms_e32(uint32_t *vd, uint32_t *vs1, uint32_t *vs2)
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{
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uint32_t res[4];
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res[0] = sig1_sha256(vs1[H4(2)]) + vs2[H4(1)] + sig0_sha256(vd[H4(1)]) +
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vd[H4(0)];
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res[1] = sig1_sha256(vs1[H4(3)]) + vs2[H4(2)] + sig0_sha256(vd[H4(2)]) +
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vd[H4(1)];
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res[2] =
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sig1_sha256(res[0]) + vs2[H4(3)] + sig0_sha256(vd[H4(3)]) + vd[H4(2)];
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res[3] =
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sig1_sha256(res[1]) + vs1[H4(0)] + sig0_sha256(vs2[H4(0)]) + vd[H4(3)];
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vd[H4(3)] = res[3];
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vd[H4(2)] = res[2];
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vd[H4(1)] = res[1];
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vd[H4(0)] = res[0];
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}
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static inline void vsha2ms_e64(uint64_t *vd, uint64_t *vs1, uint64_t *vs2)
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{
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uint64_t res[4];
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res[0] = sig1_sha512(vs1[2]) + vs2[1] + sig0_sha512(vd[1]) + vd[0];
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res[1] = sig1_sha512(vs1[3]) + vs2[2] + sig0_sha512(vd[2]) + vd[1];
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res[2] = sig1_sha512(res[0]) + vs2[3] + sig0_sha512(vd[3]) + vd[2];
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res[3] = sig1_sha512(res[1]) + vs1[0] + sig0_sha512(vs2[0]) + vd[3];
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vd[3] = res[3];
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vd[2] = res[2];
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vd[1] = res[1];
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vd[0] = res[0];
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}
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void HELPER(vsha2ms_vv)(void *vd, void *vs1, void *vs2, CPURISCVState *env,
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uint32_t desc)
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{
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uint32_t sew = FIELD_EX64(env->vtype, VTYPE, VSEW);
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uint32_t esz = sew == MO_32 ? 4 : 8;
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uint32_t total_elems;
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uint32_t vta = vext_vta(desc);
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for (uint32_t i = env->vstart / 4; i < env->vl / 4; i++) {
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if (sew == MO_32) {
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vsha2ms_e32(((uint32_t *)vd) + i * 4, ((uint32_t *)vs1) + i * 4,
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((uint32_t *)vs2) + i * 4);
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} else {
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/* If not 32 then SEW should be 64 */
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vsha2ms_e64(((uint64_t *)vd) + i * 4, ((uint64_t *)vs1) + i * 4,
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((uint64_t *)vs2) + i * 4);
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}
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}
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/* set tail elements to 1s */
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total_elems = vext_get_total_elems(env, desc, esz);
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vext_set_elems_1s(vd, vta, env->vl * esz, total_elems * esz);
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env->vstart = 0;
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}
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static inline uint64_t sum0_64(uint64_t x)
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{
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return ror64(x, 28) ^ ror64(x, 34) ^ ror64(x, 39);
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}
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static inline uint32_t sum0_32(uint32_t x)
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{
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return ror32(x, 2) ^ ror32(x, 13) ^ ror32(x, 22);
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}
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static inline uint64_t sum1_64(uint64_t x)
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{
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return ror64(x, 14) ^ ror64(x, 18) ^ ror64(x, 41);
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}
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static inline uint32_t sum1_32(uint32_t x)
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{
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return ror32(x, 6) ^ ror32(x, 11) ^ ror32(x, 25);
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}
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#define ch(x, y, z) ((x & y) ^ ((~x) & z))
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#define maj(x, y, z) ((x & y) ^ (x & z) ^ (y & z))
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static void vsha2c_64(uint64_t *vs2, uint64_t *vd, uint64_t *vs1)
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{
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uint64_t a = vs2[3], b = vs2[2], e = vs2[1], f = vs2[0];
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uint64_t c = vd[3], d = vd[2], g = vd[1], h = vd[0];
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uint64_t W0 = vs1[0], W1 = vs1[1];
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uint64_t T1 = h + sum1_64(e) + ch(e, f, g) + W0;
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uint64_t T2 = sum0_64(a) + maj(a, b, c);
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h = g;
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g = f;
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f = e;
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e = d + T1;
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d = c;
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c = b;
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b = a;
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a = T1 + T2;
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T1 = h + sum1_64(e) + ch(e, f, g) + W1;
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T2 = sum0_64(a) + maj(a, b, c);
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h = g;
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g = f;
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f = e;
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e = d + T1;
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d = c;
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c = b;
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b = a;
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a = T1 + T2;
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vd[0] = f;
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vd[1] = e;
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vd[2] = b;
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vd[3] = a;
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}
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static void vsha2c_32(uint32_t *vs2, uint32_t *vd, uint32_t *vs1)
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{
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uint32_t a = vs2[H4(3)], b = vs2[H4(2)], e = vs2[H4(1)], f = vs2[H4(0)];
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uint32_t c = vd[H4(3)], d = vd[H4(2)], g = vd[H4(1)], h = vd[H4(0)];
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uint32_t W0 = vs1[H4(0)], W1 = vs1[H4(1)];
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uint32_t T1 = h + sum1_32(e) + ch(e, f, g) + W0;
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uint32_t T2 = sum0_32(a) + maj(a, b, c);
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h = g;
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g = f;
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f = e;
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e = d + T1;
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d = c;
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c = b;
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b = a;
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a = T1 + T2;
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T1 = h + sum1_32(e) + ch(e, f, g) + W1;
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T2 = sum0_32(a) + maj(a, b, c);
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h = g;
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g = f;
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f = e;
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e = d + T1;
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d = c;
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c = b;
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b = a;
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a = T1 + T2;
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vd[H4(0)] = f;
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vd[H4(1)] = e;
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vd[H4(2)] = b;
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vd[H4(3)] = a;
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}
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void HELPER(vsha2ch32_vv)(void *vd, void *vs1, void *vs2, CPURISCVState *env,
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uint32_t desc)
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{
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const uint32_t esz = 4;
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uint32_t total_elems;
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uint32_t vta = vext_vta(desc);
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for (uint32_t i = env->vstart / 4; i < env->vl / 4; i++) {
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vsha2c_32(((uint32_t *)vs2) + 4 * i, ((uint32_t *)vd) + 4 * i,
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((uint32_t *)vs1) + 4 * i + 2);
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}
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/* set tail elements to 1s */
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total_elems = vext_get_total_elems(env, desc, esz);
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vext_set_elems_1s(vd, vta, env->vl * esz, total_elems * esz);
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env->vstart = 0;
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}
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void HELPER(vsha2ch64_vv)(void *vd, void *vs1, void *vs2, CPURISCVState *env,
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uint32_t desc)
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{
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const uint32_t esz = 8;
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uint32_t total_elems;
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uint32_t vta = vext_vta(desc);
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for (uint32_t i = env->vstart / 4; i < env->vl / 4; i++) {
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vsha2c_64(((uint64_t *)vs2) + 4 * i, ((uint64_t *)vd) + 4 * i,
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((uint64_t *)vs1) + 4 * i + 2);
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}
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/* set tail elements to 1s */
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total_elems = vext_get_total_elems(env, desc, esz);
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vext_set_elems_1s(vd, vta, env->vl * esz, total_elems * esz);
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env->vstart = 0;
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}
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void HELPER(vsha2cl32_vv)(void *vd, void *vs1, void *vs2, CPURISCVState *env,
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uint32_t desc)
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{
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const uint32_t esz = 4;
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uint32_t total_elems;
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uint32_t vta = vext_vta(desc);
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for (uint32_t i = env->vstart / 4; i < env->vl / 4; i++) {
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vsha2c_32(((uint32_t *)vs2) + 4 * i, ((uint32_t *)vd) + 4 * i,
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(((uint32_t *)vs1) + 4 * i));
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}
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/* set tail elements to 1s */
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total_elems = vext_get_total_elems(env, desc, esz);
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vext_set_elems_1s(vd, vta, env->vl * esz, total_elems * esz);
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env->vstart = 0;
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}
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void HELPER(vsha2cl64_vv)(void *vd, void *vs1, void *vs2, CPURISCVState *env,
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uint32_t desc)
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{
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uint32_t esz = 8;
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uint32_t total_elems;
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uint32_t vta = vext_vta(desc);
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for (uint32_t i = env->vstart / 4; i < env->vl / 4; i++) {
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vsha2c_64(((uint64_t *)vs2) + 4 * i, ((uint64_t *)vd) + 4 * i,
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(((uint64_t *)vs1) + 4 * i));
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}
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/* set tail elements to 1s */
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total_elems = vext_get_total_elems(env, desc, esz);
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vext_set_elems_1s(vd, vta, env->vl * esz, total_elems * esz);
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env->vstart = 0;
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}
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