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pc, pci, virtio: patches queued before 2.10
A bunch of stuff that was posted before the 2.10 timeframe, mostly fixes/cleanups. New PCI bridges. Signed-off-by: Michael S. Tsirkin <mst@redhat.com> -----BEGIN PGP SIGNATURE----- iQEcBAABAgAGBQJZspf2AAoJECgfDbjSjVRpggMIAJ7QZ0nex97iAC0MSss8meLb Rs/p9+d2DnpW/eO3sZZTuEl3bryopW1pT/0761UkHbMB5dnNKCCSXcQdeNgPECK3 TzddK8+9qI5weHv9qBJihc4cVynvFAB0sRFr1QIAanUes7XXEvPn0NOMeeXltbgU rA52sc9ksqD8QoUW377/HeXkeM/F8M/bJSR6wxMFfaMMlRUqfxkSTmeYAjk7RDT7 SMElwg2acsaZ7uP388m9nuXs7nEuYIXRaiwGet9ltXK2E8nheckm0QYVgd7jmrTa 836iWnXhik1jFmDkMkZpGfBUyfzAVgD4eofO5DLXd17JWU/sZjD3ufP9P3ng63A= =5cNH -----END PGP SIGNATURE----- Merge remote-tracking branch 'remotes/mst/tags/for_upstream' into staging pc, pci, virtio: patches queued before 2.10 A bunch of stuff that was posted before the 2.10 timeframe, mostly fixes/cleanups. New PCI bridges. Signed-off-by: Michael S. Tsirkin <mst@redhat.com> # gpg: Signature made Fri 08 Sep 2017 14:15:34 BST # gpg: using RSA key 0x281F0DB8D28D5469 # gpg: Good signature from "Michael S. Tsirkin <mst@kernel.org>" # gpg: aka "Michael S. Tsirkin <mst@redhat.com>" # Primary key fingerprint: 0270 606B 6F3C DF3D 0B17 0970 C350 3912 AFBE 8E67 # Subkey fingerprint: 5D09 FD08 71C8 F85B 94CA 8A0D 281F 0DB8 D28D 5469 * remotes/mst/tags/for_upstream: fw_cfg: rename read callback pci: add reserved slot check to do_pci_register_device() pci: move check for existing devfn into new pci_bus_devfn_available() helper vmgenid: replace x-write-pointer-available hack vhost-user-bridge: fix resume regression (since 2.9) libvhost-user: support resuming vq->last_avail_idx based on used_idx acpi/vmgenid: change device category to misc intel_iommu: fix missing BQL in pt fast path docs: update documentation considering PCIE-PCI bridge hw/pci: add QEMU-specific PCI capability to the Generic PCI Express Root Port hw/pci: introduce bridge-only vendor-specific capability to provide some hints to firmware hw/pci: introduce pcie-pci-bridge device Revert "ACPI: don't call acpi_pcihp_device_plug_cb on xen" hw/acpi: Move acpi_set_pci_info to pcihp hw/acpi: Limit hotplug to root bus on legacy mode pc: add 2.11 machine types vhost: Release memory references on cleanup Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell
commit
fcea73709b
33 changed files with 622 additions and 106 deletions
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@ -7,6 +7,8 @@ typedef struct BIOSLinker {
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GArray *file_list;
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} BIOSLinker;
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bool bios_linker_loader_can_write_pointer(void);
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BIOSLinker *bios_linker_loader_init(void);
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void bios_linker_loader_alloc(BIOSLinker *linker,
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@ -21,7 +21,6 @@ typedef struct VmGenIdState {
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DeviceClass parent_obj;
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QemuUUID guid; /* The 128-bit GUID seen by the guest */
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uint8_t vmgenid_addr_le[8]; /* Address of the GUID (little-endian) */
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bool write_pointer_available;
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} VmGenIdState;
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/* returns NULL unless there is exactly one device */
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@ -153,10 +153,6 @@
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.driver = "fw_cfg_io",\
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.property = "dma_enabled",\
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.value = "off",\
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},{\
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.driver = "vmgenid",\
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.property = "x-write-pointer-available",\
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.value = "off",\
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},
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#define HW_COMPAT_2_3 \
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@ -369,6 +369,9 @@ int e820_add_entry(uint64_t, uint64_t, uint32_t);
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int e820_get_num_entries(void);
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bool e820_get_entry(int, uint32_t, uint64_t *, uint64_t *);
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#define PC_COMPAT_2_10 \
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HW_COMPAT_2_10 \
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#define PC_COMPAT_2_9 \
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HW_COMPAT_2_9 \
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{\
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@ -192,7 +192,7 @@ int rom_add_file(const char *file, const char *fw_dir,
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MemoryRegion *rom_add_blob(const char *name, const void *blob, size_t len,
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size_t max_len, hwaddr addr,
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const char *fw_file_name,
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FWCfgReadCallback fw_callback,
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FWCfgCallback fw_callback,
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void *callback_opaque, AddressSpace *as,
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bool read_only);
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int rom_add_elf_program(const char *name, void *data, size_t datasize,
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@ -44,7 +44,7 @@ typedef struct FWCfgDmaAccess {
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uint64_t address;
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} QEMU_PACKED FWCfgDmaAccess;
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typedef void (*FWCfgReadCallback)(void *opaque);
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typedef void (*FWCfgCallback)(void *opaque);
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struct FWCfgState {
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/*< private >*/
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@ -182,7 +182,7 @@ void fw_cfg_add_file(FWCfgState *s, const char *filename, void *data,
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* fw_cfg_add_file_callback:
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* @s: fw_cfg device being modified
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* @filename: name of new fw_cfg file item
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* @callback: callback function
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* @select_cb: callback function when selecting
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* @callback_opaque: argument to be passed into callback function
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* @data: pointer to start of item data
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* @len: size of item data
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@ -201,7 +201,8 @@ void fw_cfg_add_file(FWCfgState *s, const char *filename, void *data,
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* with FW_CFG_DMA_CTL_SELECT).
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*/
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void fw_cfg_add_file_callback(FWCfgState *s, const char *filename,
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FWCfgReadCallback callback, void *callback_opaque,
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FWCfgCallback select_cb,
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void *callback_opaque,
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void *data, size_t len, bool read_only);
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/**
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@ -100,6 +100,7 @@ extern bool pci_available;
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#define PCI_DEVICE_ID_REDHAT_PXB_PCIE 0x000b
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#define PCI_DEVICE_ID_REDHAT_PCIE_RP 0x000c
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#define PCI_DEVICE_ID_REDHAT_XHCI 0x000d
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#define PCI_DEVICE_ID_REDHAT_PCIE_BRIDGE 0x000e
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#define PCI_DEVICE_ID_REDHAT_QXL 0x0100
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#define FMT_PCIBUS PRIx64
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@ -67,4 +67,29 @@ void pci_bridge_map_irq(PCIBridge *br, const char* bus_name,
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#define PCI_BRIDGE_CTL_DISCARD_STATUS 0x400 /* Discard timer status */
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#define PCI_BRIDGE_CTL_DISCARD_SERR 0x800 /* Discard timer SERR# enable */
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typedef struct PCIBridgeQemuCap {
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uint8_t id; /* Standard PCI capability header field */
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uint8_t next; /* Standard PCI capability header field */
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uint8_t len; /* Standard PCI vendor-specific capability header field */
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uint8_t type; /* Red Hat vendor-specific capability type.
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Types are defined with REDHAT_PCI_CAP_ prefix */
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uint32_t bus_res; /* Minimum number of buses to reserve */
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uint64_t io; /* IO space to reserve */
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uint32_t mem; /* Non-prefetchable memory to reserve */
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/* At most one of the following two fields may be set to a value
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* different from -1 */
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uint32_t mem_pref_32; /* Prefetchable memory to reserve (32-bit MMIO) */
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uint64_t mem_pref_64; /* Prefetchable memory to reserve (64-bit MMIO) */
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} PCIBridgeQemuCap;
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#define REDHAT_PCI_CAP_RESOURCE_RESERVE 1
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int pci_bridge_qemu_reserve_cap_init(PCIDevice *dev, int cap_offset,
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uint32_t bus_reserve, uint64_t io_reserve,
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uint32_t mem_non_pref_reserve,
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uint32_t mem_pref_32_reserve,
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uint64_t mem_pref_64_reserve,
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Error **errp);
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#endif /* QEMU_PCI_BRIDGE_H */
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@ -23,6 +23,7 @@ struct PCIBus {
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PCIIOMMUFunc iommu_fn;
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void *iommu_opaque;
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uint8_t devfn_min;
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uint32_t slot_reserved_mask;
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pci_set_irq_fn set_irq;
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pci_map_irq_fn map_irq;
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pci_route_irq_fn route_intx_to_irq;
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@ -65,6 +65,7 @@ void pcie_chassis_del_slot(PCIESlot *s);
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typedef struct PCIERootPortClass {
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PCIDeviceClass parent_class;
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DeviceRealize parent_realize;
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uint8_t (*aer_vector)(const PCIDevice *dev);
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int (*interrupts_init)(PCIDevice *dev, Error **errp);
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