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target-xtensa: implement ATOMCTL SR
ATOMCTL SR controls s32c1i opcode behavior depending on targeted memory type. See ISA, 4.3.12.4 for details. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
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536b558f58
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fcc803d119
7 changed files with 131 additions and 14 deletions
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@ -390,6 +390,7 @@ int xtensa_tlb_lookup(const CPUXtensaState *env, uint32_t addr, bool dtlb,
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static unsigned mmu_attr_to_access(uint32_t attr)
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{
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unsigned access = 0;
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if (attr < 12) {
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access |= PAGE_READ;
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if (attr & 0x1) {
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@ -398,8 +399,22 @@ static unsigned mmu_attr_to_access(uint32_t attr)
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if (attr & 0x2) {
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access |= PAGE_WRITE;
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}
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switch (attr & 0xc) {
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case 0:
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access |= PAGE_CACHE_BYPASS;
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break;
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case 4:
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access |= PAGE_CACHE_WB;
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break;
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case 8:
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access |= PAGE_CACHE_WT;
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break;
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}
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} else if (attr == 13) {
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access |= PAGE_READ | PAGE_WRITE;
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access |= PAGE_READ | PAGE_WRITE | PAGE_CACHE_ISOLATE;
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}
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return access;
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}
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@ -410,14 +425,17 @@ static unsigned mmu_attr_to_access(uint32_t attr)
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*/
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static unsigned region_attr_to_access(uint32_t attr)
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{
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unsigned access = 0;
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if ((attr < 6 && attr != 3) || attr == 14) {
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access |= PAGE_READ | PAGE_WRITE;
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}
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if (attr > 0 && attr < 6) {
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access |= PAGE_EXEC;
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}
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return access;
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static const unsigned access[16] = {
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[0] = PAGE_READ | PAGE_WRITE | PAGE_CACHE_WT,
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[1] = PAGE_READ | PAGE_WRITE | PAGE_EXEC | PAGE_CACHE_WT,
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[2] = PAGE_READ | PAGE_WRITE | PAGE_EXEC | PAGE_CACHE_BYPASS,
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[3] = PAGE_EXEC | PAGE_CACHE_WB,
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[4] = PAGE_READ | PAGE_WRITE | PAGE_EXEC | PAGE_CACHE_WB,
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[5] = PAGE_READ | PAGE_WRITE | PAGE_EXEC | PAGE_CACHE_WB,
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[14] = PAGE_READ | PAGE_WRITE | PAGE_CACHE_ISOLATE,
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};
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return access[attr & 0xf];
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}
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static bool is_access_granted(unsigned access, int is_write)
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@ -566,7 +584,7 @@ int xtensa_get_physical_addr(CPUXtensaState *env, bool update_tlb,
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} else {
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*paddr = vaddr;
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*page_size = TARGET_PAGE_SIZE;
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*access = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
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*access = PAGE_READ | PAGE_WRITE | PAGE_EXEC | PAGE_CACHE_BYPASS;
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return 0;
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}
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}
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@ -599,24 +617,34 @@ static void dump_tlb(FILE *f, fprintf_function cpu_fprintf,
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xtensa_tlb_get_entry(env, dtlb, wi, ei);
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if (entry->asid) {
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static const char * const cache_text[8] = {
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[PAGE_CACHE_BYPASS >> PAGE_CACHE_SHIFT] = "Bypass",
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[PAGE_CACHE_WT >> PAGE_CACHE_SHIFT] = "WT",
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[PAGE_CACHE_WB >> PAGE_CACHE_SHIFT] = "WB",
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[PAGE_CACHE_ISOLATE >> PAGE_CACHE_SHIFT] = "Isolate",
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};
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unsigned access = attr_to_access(entry->attr);
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unsigned cache_idx = (access & PAGE_CACHE_MASK) >>
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PAGE_CACHE_SHIFT;
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if (print_header) {
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print_header = false;
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cpu_fprintf(f, "Way %u (%d %s)\n", wi, sz, sz_text);
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cpu_fprintf(f,
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"\tVaddr Paddr ASID Attr RWX\n"
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"\t---------- ---------- ---- ---- ---\n");
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"\tVaddr Paddr ASID Attr RWX Cache\n"
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"\t---------- ---------- ---- ---- --- -------\n");
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}
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cpu_fprintf(f,
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"\t0x%08x 0x%08x 0x%02x 0x%02x %c%c%c\n",
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"\t0x%08x 0x%08x 0x%02x 0x%02x %c%c%c %-7s\n",
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entry->vaddr,
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entry->paddr,
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entry->asid,
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entry->attr,
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(access & PAGE_READ) ? 'R' : '-',
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(access & PAGE_WRITE) ? 'W' : '-',
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(access & PAGE_EXEC) ? 'X' : '-');
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(access & PAGE_EXEC) ? 'X' : '-',
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cache_text[cache_idx] ? cache_text[cache_idx] :
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"Invalid");
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}
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}
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}
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