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Header cleanup patches for 2023-01-20

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Merge tag 'pull-include-2023-01-20' of https://repo.or.cz/qemu/armbru into staging

Header cleanup patches for 2023-01-20

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# gpg: Signature made Fri 20 Jan 2023 06:41:42 GMT
# gpg:                using RSA key 354BC8B3D7EB2A6B68674E5F3870B400EB918653
# gpg:                issuer "armbru@redhat.com"
# gpg: Good signature from "Markus Armbruster <armbru@redhat.com>" [full]
# gpg:                 aka "Markus Armbruster <armbru@pond.sub.org>" [full]
# Primary key fingerprint: 354B C8B3 D7EB 2A6B 6867  4E5F 3870 B400 EB91 8653

* tag 'pull-include-2023-01-20' of https://repo.or.cz/qemu/armbru:
  include/hw/ppc include/hw/pci-host: Drop extra typedefs
  include/hw/ppc: Don't include hw/pci-host/pnv_phb.h from pnv.h
  include/hw/ppc: Supply a few missing includes
  include/hw/ppc: Split pnv_chip.h off pnv.h
  include/hw/block: Include hw/block/block.h where needed
  hw/sparc64/niagara: Use blk_name() instead of open-coding it
  include/block: Untangle inclusion loops
  coroutine: Use Coroutine typedef name instead of structure tag
  coroutine: Split qemu/coroutine-core.h off qemu/coroutine.h
  coroutine: Clean up superfluous inclusion of qemu/lockable.h
  coroutine: Move coroutine_fn to qemu/osdep.h, trim includes
  coroutine: Clean up superfluous inclusion of qemu/coroutine.h

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell 2023-01-20 13:17:54 +00:00
commit fcb7e040f5
141 changed files with 494 additions and 344 deletions
Download patch file Download diff file Expand all files Collapse all files

9
include/block/aio.h
View file

@ -17,7 +17,7 @@
#ifdef CONFIG_LINUX_IO_URING
#include <liburing.h>
#endif
#include "qemu/coroutine.h"
#include "qemu/coroutine-core.h"
#include "qemu/queue.h"
#include "qemu/event_notifier.h"
#include "qemu/thread.h"
@ -52,7 +52,6 @@ typedef void QEMUBHFunc(void *opaque);
typedef bool AioPollFn(void *opaque);
typedef void IOHandler(void *opaque);
struct Coroutine;
struct ThreadPool;
struct LinuxAioState;
struct LuringState;
@ -694,7 +693,7 @@ static inline bool aio_node_check(AioContext *ctx, bool is_external)
* is the context in which the coroutine is running (i.e. the value of
* qemu_get_current_aio_context() from the coroutine itself).
*/
void aio_co_schedule(AioContext *ctx, struct Coroutine *co);
void aio_co_schedule(AioContext *ctx, Coroutine *co);
/**
* aio_co_reschedule_self:
@ -717,7 +716,7 @@ void coroutine_fn aio_co_reschedule_self(AioContext *new_ctx);
* context. The coroutine must not be entered by anyone else while
* aio_co_wake() is active.
*/
void aio_co_wake(struct Coroutine *co);
void aio_co_wake(Coroutine *co);
/**
* aio_co_enter:
@ -726,7 +725,7 @@ void aio_co_wake(struct Coroutine *co);
*
* Enter a coroutine in the specified AioContext.
*/
void aio_co_enter(AioContext *ctx, struct Coroutine *co);
void aio_co_enter(AioContext *ctx, Coroutine *co);
/**
* Return the AioContext whose event loop runs in the current thread.

2
include/block/aio_task.h
View file

@ -25,8 +25,6 @@
#ifndef BLOCK_AIO_TASK_H
#define BLOCK_AIO_TASK_H
#include "qemu/coroutine.h"
typedef struct AioTaskPool AioTaskPool;
typedef struct AioTask AioTask;
typedef int coroutine_fn (*AioTaskFunc)(AioTask *task);

10
include/block/block-common.h
View file

@ -24,13 +24,8 @@
#ifndef BLOCK_COMMON_H
#define BLOCK_COMMON_H
#include "block/aio.h"
#include "block/aio-wait.h"
#include "qemu/iov.h"
#include "qemu/coroutine.h"
#include "block/accounting.h"
#include "qemu/hbitmap.h"
#include "qemu/transactions.h"
#include "qapi/qapi-types-block-core.h"
#include "qemu/queue.h"
/*
* co_wrapper{*}: Function specifiers used by block-coroutine-wrapper.py
@ -56,7 +51,6 @@
#define co_wrapper_bdrv_rdlock
#define co_wrapper_mixed_bdrv_rdlock
#include "block/dirty-bitmap.h"
#include "block/blockjob.h"
/* block.c */

4
include/block/block-copy.h
View file

@ -15,8 +15,8 @@
#ifndef BLOCK_COPY_H
#define BLOCK_COPY_H
#include "block/block.h"
#include "qemu/co-shared-resource.h"
#include "block/block-common.h"
#include "qemu/progress_meter.h"
/* All APIs are thread-safe */

4
include/block/block-global-state.h
View file

@ -24,7 +24,9 @@
#ifndef BLOCK_GLOBAL_STATE_H
#define BLOCK_GLOBAL_STATE_H
#include "block-common.h"
#include "block/block-common.h"
#include "qemu/coroutine.h"
#include "qemu/transactions.h"
/*
* Global state (GS) API. These functions run under the BQL.

2
include/block/block-hmp-cmds.h
View file

@ -15,6 +15,8 @@
#ifndef BLOCK_BLOCK_HMP_CMDS_H
#define BLOCK_BLOCK_HMP_CMDS_H
#include "qemu/coroutine.h"
void hmp_drive_add(Monitor *mon, const QDict *qdict);
void hmp_commit(Monitor *mon, const QDict *qdict);

5
include/block/block-io.h
View file

@ -24,7 +24,10 @@
#ifndef BLOCK_IO_H
#define BLOCK_IO_H
#include "block-common.h"
#include "block/aio-wait.h"
#include "block/block-common.h"
#include "qemu/coroutine.h"
#include "qemu/iov.h"
/*
* I/O API functions. These functions are thread-safe, and therefore

4
include/block/block.h
View file

@ -24,8 +24,8 @@
#ifndef BLOCK_H
#define BLOCK_H
#include "block-global-state.h"
#include "block-io.h"
#include "block/block-global-state.h"
#include "block/block-io.h"
/* DO NOT ADD ANYTHING IN HERE. USE ONE OF THE HEADERS INCLUDED ABOVE */

2
include/block/block_backup.h
View file

@ -18,7 +18,7 @@
#ifndef BLOCK_BACKUP_H
#define BLOCK_BACKUP_H
#include "block/block_int.h"
#include "block/blockjob.h"
void backup_do_checkpoint(BlockJob *job, Error **errp);

14
include/block/block_int-common.h
View file

@ -24,17 +24,13 @@
#ifndef BLOCK_INT_COMMON_H
#define BLOCK_INT_COMMON_H
#include "block/accounting.h"
#include "block/block.h"
#include "block/aio-wait.h"
#include "qemu/queue.h"
#include "qemu/coroutine.h"
#include "qemu/stats64.h"
#include "qemu/timer.h"
#include "qemu/hbitmap.h"
#include "block/aio.h"
#include "block/block-common.h"
#include "block/block-global-state.h"
#include "block/snapshot.h"
#include "qemu/throttle.h"
#include "qemu/iov.h"
#include "qemu/rcu.h"
#include "qemu/stats64.h"
#define BLOCK_FLAG_LAZY_REFCOUNTS 8

5
include/block/block_int-global-state.h
View file

@ -25,7 +25,10 @@
#ifndef BLOCK_INT_GLOBAL_STATE_H
#define BLOCK_INT_GLOBAL_STATE_H
#include "block_int-common.h"
#include "block/blockjob.h"
#include "block/block_int-common.h"
#include "qemu/hbitmap.h"
#include "qemu/main-loop.h"
/*
* Global state (GS) API. These functions run under the BQL.

4
include/block/block_int-io.h
View file

@ -24,7 +24,9 @@
#ifndef BLOCK_INT_IO_H
#define BLOCK_INT_IO_H
#include "block_int-common.h"
#include "block/block_int-common.h"
#include "qemu/hbitmap.h"
#include "qemu/main-loop.h"
/*
* I/O API functions. These functions are thread-safe.

4
include/block/block_int.h
View file

@ -24,8 +24,8 @@
#ifndef BLOCK_INT_H
#define BLOCK_INT_H
#include "block_int-global-state.h"
#include "block_int-io.h"
#include "block/block_int-global-state.h"
#include "block/block_int-io.h"
#include "block/graph-lock.h"
/* DO NOT ADD ANYTHING IN HERE. USE ONE OF THE HEADERS INCLUDED ABOVE */

2
include/block/blockjob.h
View file

@ -26,8 +26,8 @@
#ifndef BLOCKJOB_H
#define BLOCKJOB_H
#include "qapi/qapi-types-block-core.h"
#include "qemu/job.h"
#include "block/block.h"
#include "qemu/ratelimit.h"
#define BLOCK_JOB_SLICE_TIME 100000000ULL /* ns */

1
include/block/blockjob_int.h
View file

@ -27,7 +27,6 @@
#define BLOCKJOB_INT_H
#include "block/blockjob.h"
#include "block/block.h"
/**
* BlockJobDriver:

1
include/block/dirty-bitmap.h
View file

@ -1,6 +1,7 @@
#ifndef BLOCK_DIRTY_BITMAP_H
#define BLOCK_DIRTY_BITMAP_H
#include "block/block-common.h"
#include "qapi/qapi-types-block-core.h"
#include "qemu/hbitmap.h"

2
include/block/graph-lock.h
View file

@ -23,8 +23,6 @@
#include "qemu/osdep.h"
#include "qemu/clang-tsa.h"
#include "qemu/coroutine.h"
/**
* Graph Lock API
* This API provides a rwlock used to protect block layer

2
include/block/qapi.h
View file

@ -25,8 +25,8 @@
#ifndef BLOCK_QAPI_H
#define BLOCK_QAPI_H
#include "block/block.h"
#include "block/snapshot.h"
#include "qapi/qapi-types-block-core.h"
BlockDeviceInfo *bdrv_block_device_info(BlockBackend *blk,
BlockDriverState *bs,

1
include/block/raw-aio.h
View file

@ -17,7 +17,6 @@
#define QEMU_RAW_AIO_H
#include "block/aio.h"
#include "qemu/coroutine.h"
#include "qemu/iov.h"
/* AIO request types */

2
include/block/thread-pool.h
View file

@ -18,7 +18,7 @@
#ifndef QEMU_THREAD_POOL_H
#define QEMU_THREAD_POOL_H
#include "block/block.h"
#include "block/aio.h"
#define THREAD_POOL_MAX_THREADS_DEFAULT 64

2
include/block/throttle-groups.h
View file

@ -25,8 +25,8 @@
#ifndef THROTTLE_GROUPS_H
#define THROTTLE_GROUPS_H
#include "qemu/coroutine.h"
#include "qemu/throttle.h"
#include "block/block_int.h"
#include "qom/object.h"
/* The ThrottleGroupMember structure indicates membership in a ThrottleGroup

1
include/hw/block/swim.h
View file

@ -11,6 +11,7 @@
#ifndef SWIM_H
#define SWIM_H
#include "hw/block/block.h"
#include "hw/sysbus.h"
#include "qom/object.h"

1
include/hw/pci-host/pnv_phb3.h
View file

@ -15,7 +15,6 @@
#include "hw/pci-host/pnv_phb.h"
typedef struct PnvPHB3 PnvPHB3;
typedef struct PnvChip PnvChip;
/*
* PHB3 XICS Source for MSIs

5
include/hw/pci-host/pnv_phb4.h
View file

@ -10,15 +10,14 @@
#ifndef PCI_HOST_PNV_PHB4_H
#define PCI_HOST_PNV_PHB4_H
#include "hw/pci-host/pnv_phb.h"
#include "hw/pci/pci_bus.h"
#include "hw/ppc/pnv.h"
#include "hw/ppc/xive.h"
#include "qom/object.h"
typedef struct PnvPhb4PecState PnvPhb4PecState;
typedef struct PnvPhb4PecStack PnvPhb4PecStack;
typedef struct PnvPHB4 PnvPHB4;
typedef struct PnvPHB PnvPHB;
typedef struct PnvChip PnvChip;
/*
* We have one such address space wrapper per possible device under

146
include/hw/ppc/pnv.h
View file

@ -20,158 +20,18 @@
#ifndef PPC_PNV_H
#define PPC_PNV_H
#include "cpu.h"
#include "hw/boards.h"
#include "hw/sysbus.h"
#include "hw/ipmi/ipmi.h"
#include "hw/ppc/pnv_lpc.h"
#include "hw/ppc/pnv_pnor.h"
#include "hw/ppc/pnv_psi.h"
#include "hw/ppc/pnv_occ.h"
#include "hw/ppc/pnv_sbe.h"
#include "hw/ppc/pnv_homer.h"
#include "hw/ppc/pnv_xive.h"
#include "hw/ppc/pnv_core.h"
#include "hw/pci-host/pnv_phb3.h"
#include "hw/pci-host/pnv_phb4.h"
#include "hw/pci-host/pnv_phb.h"
#include "qom/object.h"
#define TYPE_PNV_CHIP "pnv-chip"
OBJECT_DECLARE_TYPE(PnvChip, PnvChipClass,
PNV_CHIP)
struct PnvChip {
/*< private >*/
SysBusDevice parent_obj;
/*< public >*/
uint32_t chip_id;
uint64_t ram_start;
uint64_t ram_size;
uint32_t nr_cores;
uint32_t nr_threads;
uint64_t cores_mask;
PnvCore **cores;
uint32_t num_pecs;
MemoryRegion xscom_mmio;
MemoryRegion xscom;
AddressSpace xscom_as;
MemoryRegion *fw_mr;
gchar *dt_isa_nodename;
};
#define TYPE_PNV8_CHIP "pnv8-chip"
typedef struct PnvChip PnvChip;
typedef struct Pnv8Chip Pnv8Chip;
DECLARE_INSTANCE_CHECKER(Pnv8Chip, PNV8_CHIP,
TYPE_PNV8_CHIP)
struct Pnv8Chip {
/*< private >*/
PnvChip parent_obj;
/*< public >*/
MemoryRegion icp_mmio;
PnvLpcController lpc;
Pnv8Psi psi;
PnvOCC occ;
PnvHomer homer;
#define PNV8_CHIP_PHB3_MAX 4
/*
* The array is used to allow quick access to the phbs by
* pnv_ics_get_child() and pnv_ics_resend_child().
*/
PnvPHB *phbs[PNV8_CHIP_PHB3_MAX];
uint32_t num_phbs;
XICSFabric *xics;
};
#define TYPE_PNV9_CHIP "pnv9-chip"
typedef struct Pnv9Chip Pnv9Chip;
DECLARE_INSTANCE_CHECKER(Pnv9Chip, PNV9_CHIP,
TYPE_PNV9_CHIP)
struct Pnv9Chip {
/*< private >*/
PnvChip parent_obj;
/*< public >*/
PnvXive xive;
Pnv9Psi psi;
PnvLpcController lpc;
PnvOCC occ;
PnvSBE sbe;
PnvHomer homer;
uint32_t nr_quads;
PnvQuad *quads;
#define PNV9_CHIP_MAX_PEC 3
PnvPhb4PecState pecs[PNV9_CHIP_MAX_PEC];
};
/*
* A SMT8 fused core is a pair of SMT4 cores.
*/
#define PNV9_PIR2FUSEDCORE(pir) (((pir) >> 3) & 0xf)
#define PNV9_PIR2CHIP(pir) (((pir) >> 8) & 0x7f)
#define TYPE_PNV10_CHIP "pnv10-chip"
typedef struct Pnv10Chip Pnv10Chip;
DECLARE_INSTANCE_CHECKER(Pnv10Chip, PNV10_CHIP,
TYPE_PNV10_CHIP)
struct Pnv10Chip {
/*< private >*/
PnvChip parent_obj;
/*< public >*/
PnvXive2 xive;
Pnv9Psi psi;
PnvLpcController lpc;
PnvOCC occ;
PnvSBE sbe;
PnvHomer homer;
uint32_t nr_quads;
PnvQuad *quads;
#define PNV10_CHIP_MAX_PEC 2
PnvPhb4PecState pecs[PNV10_CHIP_MAX_PEC];
};
#define PNV10_PIR2FUSEDCORE(pir) (((pir) >> 3) & 0xf)
#define PNV10_PIR2CHIP(pir) (((pir) >> 8) & 0x7f)
struct PnvChipClass {
/*< private >*/
SysBusDeviceClass parent_class;
/*< public >*/
uint64_t chip_cfam_id;
uint64_t cores_mask;
uint32_t num_pecs;
uint32_t num_phbs;
DeviceRealize parent_realize;
uint32_t (*core_pir)(PnvChip *chip, uint32_t core_id);
void (*intc_create)(PnvChip *chip, PowerPCCPU *cpu, Error **errp);
void (*intc_reset)(PnvChip *chip, PowerPCCPU *cpu);
void (*intc_destroy)(PnvChip *chip, PowerPCCPU *cpu);
void (*intc_print_info)(PnvChip *chip, PowerPCCPU *cpu, Monitor *mon);
ISABus *(*isa_create)(PnvChip *chip, Error **errp);
void (*dt_populate)(PnvChip *chip, void *fdt);
void (*pic_print_info)(PnvChip *chip, Monitor *mon);
uint64_t (*xscom_core_base)(PnvChip *chip, uint32_t core_id);
uint32_t (*xscom_pcba)(PnvChip *chip, uint64_t addr);
};
#define PNV_CHIP_TYPE_SUFFIX "-" TYPE_PNV_CHIP
#define PNV_CHIP_TYPE_NAME(cpu_model) cpu_model PNV_CHIP_TYPE_SUFFIX
@ -198,6 +58,8 @@ DECLARE_INSTANCE_CHECKER(PnvChip, PNV_CHIP_POWER10,
PowerPCCPU *pnv_chip_find_cpu(PnvChip *chip, uint32_t pir);
typedef struct PnvPHB PnvPHB;
#define TYPE_PNV_MACHINE MACHINE_TYPE_NAME("powernv")
typedef struct PnvMachineClass PnvMachineClass;
typedef struct PnvMachineState PnvMachineState;

147
include/hw/ppc/pnv_chip.h Normal file
View file

@ -0,0 +1,147 @@
#ifndef PPC_PNV_CHIP_H
#define PPC_PNV_CHIP_H
#include "hw/pci-host/pnv_phb4.h"
#include "hw/ppc/pnv_core.h"
#include "hw/ppc/pnv_homer.h"
#include "hw/ppc/pnv_lpc.h"
#include "hw/ppc/pnv_occ.h"
#include "hw/ppc/pnv_psi.h"
#include "hw/ppc/pnv_sbe.h"
#include "hw/ppc/pnv_xive.h"
#include "hw/sysbus.h"
OBJECT_DECLARE_TYPE(PnvChip, PnvChipClass,
PNV_CHIP)
struct PnvChip {
/*< private >*/
SysBusDevice parent_obj;
/*< public >*/
uint32_t chip_id;
uint64_t ram_start;
uint64_t ram_size;
uint32_t nr_cores;
uint32_t nr_threads;
uint64_t cores_mask;
PnvCore **cores;
uint32_t num_pecs;
MemoryRegion xscom_mmio;
MemoryRegion xscom;
AddressSpace xscom_as;
MemoryRegion *fw_mr;
gchar *dt_isa_nodename;
};
#define TYPE_PNV8_CHIP "pnv8-chip"
DECLARE_INSTANCE_CHECKER(Pnv8Chip, PNV8_CHIP,
TYPE_PNV8_CHIP)
struct Pnv8Chip {
/*< private >*/
PnvChip parent_obj;
/*< public >*/
MemoryRegion icp_mmio;
PnvLpcController lpc;
Pnv8Psi psi;
PnvOCC occ;
PnvHomer homer;
#define PNV8_CHIP_PHB3_MAX 4
/*
* The array is used to allow quick access to the phbs by
* pnv_ics_get_child() and pnv_ics_resend_child().
*/
PnvPHB *phbs[PNV8_CHIP_PHB3_MAX];
uint32_t num_phbs;
XICSFabric *xics;
};
#define TYPE_PNV9_CHIP "pnv9-chip"
DECLARE_INSTANCE_CHECKER(Pnv9Chip, PNV9_CHIP,
TYPE_PNV9_CHIP)
struct Pnv9Chip {
/*< private >*/
PnvChip parent_obj;
/*< public >*/
PnvXive xive;
Pnv9Psi psi;
PnvLpcController lpc;
PnvOCC occ;
PnvSBE sbe;
PnvHomer homer;
uint32_t nr_quads;
PnvQuad *quads;
#define PNV9_CHIP_MAX_PEC 3
PnvPhb4PecState pecs[PNV9_CHIP_MAX_PEC];
};
/*
* A SMT8 fused core is a pair of SMT4 cores.
*/
#define PNV9_PIR2FUSEDCORE(pir) (((pir) >> 3) & 0xf)
#define PNV9_PIR2CHIP(pir) (((pir) >> 8) & 0x7f)
#define TYPE_PNV10_CHIP "pnv10-chip"
DECLARE_INSTANCE_CHECKER(Pnv10Chip, PNV10_CHIP,
TYPE_PNV10_CHIP)
struct Pnv10Chip {
/*< private >*/
PnvChip parent_obj;
/*< public >*/
PnvXive2 xive;
Pnv9Psi psi;
PnvLpcController lpc;
PnvOCC occ;
PnvSBE sbe;
PnvHomer homer;
uint32_t nr_quads;
PnvQuad *quads;
#define PNV10_CHIP_MAX_PEC 2
PnvPhb4PecState pecs[PNV10_CHIP_MAX_PEC];
};
#define PNV10_PIR2FUSEDCORE(pir) (((pir) >> 3) & 0xf)
#define PNV10_PIR2CHIP(pir) (((pir) >> 8) & 0x7f)
struct PnvChipClass {
/*< private >*/
SysBusDeviceClass parent_class;
/*< public >*/
uint64_t chip_cfam_id;
uint64_t cores_mask;
uint32_t num_pecs;
uint32_t num_phbs;
DeviceRealize parent_realize;
uint32_t (*core_pir)(PnvChip *chip, uint32_t core_id);
void (*intc_create)(PnvChip *chip, PowerPCCPU *cpu, Error **errp);
void (*intc_reset)(PnvChip *chip, PowerPCCPU *cpu);
void (*intc_destroy)(PnvChip *chip, PowerPCCPU *cpu);
void (*intc_print_info)(PnvChip *chip, PowerPCCPU *cpu, Monitor *mon);
ISABus *(*isa_create)(PnvChip *chip, Error **errp);
void (*dt_populate)(PnvChip *chip, void *fdt);
void (*pic_print_info)(PnvChip *chip, Monitor *mon);
uint64_t (*xscom_core_base)(PnvChip *chip, uint32_t core_id);
uint32_t (*xscom_pcba)(PnvChip *chip, uint64_t addr);
};
#endif

3
include/hw/ppc/pnv_core.h
View file

@ -22,14 +22,13 @@
#include "hw/cpu/core.h"
#include "target/ppc/cpu.h"
#include "hw/ppc/pnv.h"
#include "qom/object.h"
#define TYPE_PNV_CORE "powernv-cpu-core"
OBJECT_DECLARE_TYPE(PnvCore, PnvCoreClass,
PNV_CORE)
typedef struct PnvChip PnvChip;
struct PnvCore {
/*< private >*/
CPUCore parent_obj;

2
include/hw/ppc/pnv_homer.h
View file

@ -39,7 +39,7 @@ DECLARE_INSTANCE_CHECKER(PnvHomer, PNV10_HOMER,
struct PnvHomer {
DeviceState parent;
struct PnvChip *chip;
PnvChip *chip;
MemoryRegion pba_regs;
MemoryRegion regs;
};

11
include/hw/ppc/pnv_lpc.h
View file

@ -20,7 +20,9 @@
#ifndef PPC_PNV_LPC_H
#define PPC_PNV_LPC_H
#include "qom/object.h"
#include "exec/memory.h"
#include "hw/ppc/pnv.h"
#include "hw/qdev-core.h"
#define TYPE_PNV_LPC "pnv-lpc"
typedef struct PnvLpcClass PnvLpcClass;
@ -92,13 +94,8 @@ struct PnvLpcClass {
DeviceRealize parent_realize;
};
/*
* Old compilers error on typdef forward declarations. Keep them happy.
*/
struct PnvChip;
ISABus *pnv_lpc_isa_create(PnvLpcController *lpc, bool use_cpld, Error **errp);
int pnv_dt_lpc(struct PnvChip *chip, void *fdt, int root_offset,
int pnv_dt_lpc(PnvChip *chip, void *fdt, int root_offset,
uint64_t lpcm_addr, uint64_t lpcm_size);
#endif /* PPC_PNV_LPC_H */

3
include/hw/ppc/pnv_occ.h
View file

@ -20,7 +20,8 @@
#ifndef PPC_PNV_OCC_H
#define PPC_PNV_OCC_H
#include "qom/object.h"
#include "exec/memory.h"
#include "hw/qdev-core.h"
#define TYPE_PNV_OCC "pnv-occ"
OBJECT_DECLARE_TYPE(PnvOCC, PnvOCCClass,

2
include/hw/ppc/pnv_pnor.h
View file

@ -10,7 +10,7 @@
#ifndef PPC_PNV_PNOR_H
#define PPC_PNV_PNOR_H
#include "qom/object.h"
#include "hw/sysbus.h"
/*
* PNOR offset on the LPC FW address space

3
include/hw/ppc/pnv_sbe.h
View file

@ -20,7 +20,8 @@
#ifndef PPC_PNV_SBE_H
#define PPC_PNV_SBE_H
#include "qom/object.h"
#include "exec/memory.h"
#include "hw/qdev-core.h"
#define TYPE_PNV_SBE "pnv-sbe"
OBJECT_DECLARE_TYPE(PnvSBE, PnvSBEClass, PNV_SBE)

7
include/hw/ppc/pnv_xive.h
View file

@ -10,12 +10,11 @@
#ifndef PPC_PNV_XIVE_H
#define PPC_PNV_XIVE_H
#include "hw/ppc/pnv.h"
#include "hw/ppc/xive.h"
#include "qom/object.h"
#include "hw/ppc/xive2.h"
struct PnvChip;
#define TYPE_PNV_XIVE "pnv-xive"
OBJECT_DECLARE_TYPE(PnvXive, PnvXiveClass,
PNV_XIVE)
@ -31,7 +30,7 @@ struct PnvXive {
XiveRouter parent_obj;
/* Owning chip */
struct PnvChip *chip;
PnvChip *chip;
/* XSCOM addresses giving access to the controller registers */
MemoryRegion xscom_regs;
@ -106,7 +105,7 @@ typedef struct PnvXive2 {
Xive2Router parent_obj;
/* Owning chip */
struct PnvChip *chip;
PnvChip *chip;
/* XSCOM addresses giving access to the controller registers */
MemoryRegion xscom_regs;

3
include/hw/ppc/pnv_xscom.h
View file

@ -20,7 +20,8 @@
#ifndef PPC_PNV_XSCOM_H
#define PPC_PNV_XSCOM_H
#include "qom/object.h"
#include "exec/memory.h"
#include "hw/ppc/pnv.h"
typedef struct PnvXScomInterface PnvXScomInterface;

2
include/hw/ppc/xive2.h
View file

@ -11,7 +11,9 @@
#ifndef PPC_XIVE2_H
#define PPC_XIVE2_H
#include "hw/ppc/xive.h"
#include "hw/ppc/xive2_regs.h"
#include "hw/sysbus.h"
/*
* XIVE2 Router (POWER10)

2
include/hw/ppc/xive2_regs.h
View file

@ -10,6 +10,8 @@
#ifndef PPC_XIVE2_REGS_H
#define PPC_XIVE2_REGS_H
#include "cpu.h"
/*
* Thread Interrupt Management Area (TIMA)
*

2
include/io/channel.h
View file

@ -22,7 +22,7 @@
#define QIO_CHANNEL_H
#include "qom/object.h"
#include "qemu/coroutine.h"
#include "qemu/coroutine-core.h"
#include "block/aio.h"
#define TYPE_QIO_CHANNEL "qio-channel"

1
include/monitor/hmp.h
View file

@ -15,7 +15,6 @@
#define HMP_H
#include "qemu/readline.h"
#include "qemu/coroutine.h"
#include "qapi/qapi-types-common.h"
bool hmp_handle_error(Monitor *mon, Error *err);

154
include/qemu/coroutine-core.h Normal file
View file

@ -0,0 +1,154 @@
/*
* QEMU coroutine implementation
*
* Copyright IBM, Corp. 2011
*
* Authors:
* Stefan Hajnoczi <stefanha@linux.vnet.ibm.com>
* Kevin Wolf <kwolf@redhat.com>
*
* This work is licensed under the terms of the GNU LGPL, version 2 or later.
* See the COPYING.LIB file in the top-level directory.
*
*/
#ifndef QEMU_COROUTINE_CORE_H
#define QEMU_COROUTINE_CORE_H
/**
* Coroutines are a mechanism for stack switching and can be used for
* cooperative userspace threading. These functions provide a simple but
* useful flavor of coroutines that is suitable for writing sequential code,
* rather than callbacks, for operations that need to give up control while
* waiting for events to complete.
*
* These functions are re-entrant and may be used outside the global mutex.
*
* Functions that execute in coroutine context cannot be called
* directly from normal functions. Use @coroutine_fn to mark such
* functions. For example:
*
* static void coroutine_fn foo(void) {
* ....
* }
*
* In the future it would be nice to have the compiler or a static
* checker catch misuse of such functions. This annotation might make
* it possible and in the meantime it serves as documentation.
*/
/**
* Mark a function that executes in coroutine context
*
*
* Functions that execute in coroutine context cannot be called
* directly from normal functions. Use @coroutine_fn to mark such
* functions. For example:
*
* static void coroutine_fn foo(void) {
* ....
* }
*
* In the future it would be nice to have the compiler or a static
* checker catch misuse of such functions. This annotation might make
* it possible and in the meantime it serves as documentation.
*/
typedef struct Coroutine Coroutine;
typedef struct CoMutex CoMutex;
/**
* Coroutine entry point
*
* When the coroutine is entered for the first time, opaque is passed in as an
* argument.
*
* When this function returns, the coroutine is destroyed automatically and
* execution continues in the caller who last entered the coroutine.
*/
typedef void coroutine_fn CoroutineEntry(void *opaque);
/**
* Create a new coroutine
*
* Use qemu_coroutine_enter() to actually transfer control to the coroutine.
* The opaque argument is passed as the argument to the entry point.
*/
Coroutine *qemu_coroutine_create(CoroutineEntry *entry, void *opaque);
/**
* Transfer control to a coroutine
*/
void qemu_coroutine_enter(Coroutine *coroutine);
/**
* Transfer control to a coroutine if it's not active (i.e. part of the call
* stack of the running coroutine). Otherwise, do nothing.
*/
void qemu_coroutine_enter_if_inactive(Coroutine *co);
/**
* Transfer control to a coroutine and associate it with ctx
*/
void qemu_aio_coroutine_enter(AioContext *ctx, Coroutine *co);
/**
* Transfer control back to a coroutine's caller
*
* This function does not return until the coroutine is re-entered using
* qemu_coroutine_enter().
*/
void coroutine_fn qemu_coroutine_yield(void);
/**
* Get the AioContext of the given coroutine
*/
AioContext *qemu_coroutine_get_aio_context(Coroutine *co);
/**
* Get the currently executing coroutine
*/
Coroutine *qemu_coroutine_self(void);
/**
* Return whether or not currently inside a coroutine
*
* This can be used to write functions that work both when in coroutine context
* and when not in coroutine context. Note that such functions cannot use the
* coroutine_fn annotation since they work outside coroutine context.
*/
bool qemu_in_coroutine(void);
/**
* Return true if the coroutine is currently entered
*
* A coroutine is "entered" if it has not yielded from the current
* qemu_coroutine_enter() call used to run it. This does not mean that the
* coroutine is currently executing code since it may have transferred control
* to another coroutine using qemu_coroutine_enter().
*
* When several coroutines enter each other there may be no way to know which
* ones have already been entered. In such situations this function can be
* used to avoid recursively entering coroutines.
*/
bool qemu_coroutine_entered(Coroutine *co);
/**
* Initialises a CoMutex. This must be called before any other operation is used
* on the CoMutex.
*/
void qemu_co_mutex_init(CoMutex *mutex);
/**
* Locks the mutex. If the lock cannot be taken immediately, control is
* transferred to the caller of the current coroutine.
*/
void coroutine_fn qemu_co_mutex_lock(CoMutex *mutex);
/**
* Unlocks the mutex and schedules the next coroutine that was waiting for this
* lock to be run.
*/
void coroutine_fn qemu_co_mutex_unlock(CoMutex *mutex);
#endif

113
include/qemu/coroutine.h
View file

@ -15,6 +15,7 @@
#ifndef QEMU_COROUTINE_H
#define QEMU_COROUTINE_H
#include "qemu/coroutine-core.h"
#include "qemu/queue.h"
#include "qemu/timer.h"
@ -26,101 +27,19 @@
* waiting for events to complete.
*
* These functions are re-entrant and may be used outside the global mutex.
*/
/**
* Mark a function that executes in coroutine context
*
* Functions that execute in coroutine context cannot be called directly from
* normal functions. In the future it would be nice to enable compiler or
* static checker support for catching such errors. This annotation might make
* it possible and in the meantime it serves as documentation.
*
* For example:
* Functions that execute in coroutine context cannot be called
* directly from normal functions. Use @coroutine_fn to mark such
* functions. For example:
*
* static void coroutine_fn foo(void) {
* ....
* }
*/
#define coroutine_fn
typedef struct Coroutine Coroutine;
/**
* Coroutine entry point
*
* When the coroutine is entered for the first time, opaque is passed in as an
* argument.
*
* When this function returns, the coroutine is destroyed automatically and
* execution continues in the caller who last entered the coroutine.
* In the future it would be nice to have the compiler or a static
* checker catch misuse of such functions. This annotation might make
* it possible and in the meantime it serves as documentation.
*/
typedef void coroutine_fn CoroutineEntry(void *opaque);
/**
* Create a new coroutine
*
* Use qemu_coroutine_enter() to actually transfer control to the coroutine.
* The opaque argument is passed as the argument to the entry point.
*/
Coroutine *qemu_coroutine_create(CoroutineEntry *entry, void *opaque);
/**
* Transfer control to a coroutine
*/
void qemu_coroutine_enter(Coroutine *coroutine);
/**
* Transfer control to a coroutine if it's not active (i.e. part of the call
* stack of the running coroutine). Otherwise, do nothing.
*/
void qemu_coroutine_enter_if_inactive(Coroutine *co);
/**
* Transfer control to a coroutine and associate it with ctx
*/
void qemu_aio_coroutine_enter(AioContext *ctx, Coroutine *co);
/**
* Transfer control back to a coroutine's caller
*
* This function does not return until the coroutine is re-entered using
* qemu_coroutine_enter().
*/
void coroutine_fn qemu_coroutine_yield(void);
/**
* Get the AioContext of the given coroutine
*/
AioContext *qemu_coroutine_get_aio_context(Coroutine *co);
/**
* Get the currently executing coroutine
*/
Coroutine *qemu_coroutine_self(void);
/**
* Return whether or not currently inside a coroutine
*
* This can be used to write functions that work both when in coroutine context
* and when not in coroutine context. Note that such functions cannot use the
* coroutine_fn annotation since they work outside coroutine context.
*/
bool qemu_in_coroutine(void);
/**
* Return true if the coroutine is currently entered
*
* A coroutine is "entered" if it has not yielded from the current
* qemu_coroutine_enter() call used to run it. This does not mean that the
* coroutine is currently executing code since it may have transferred control
* to another coroutine using qemu_coroutine_enter().
*
* When several coroutines enter each other there may be no way to know which
* ones have already been entered. In such situations this function can be
* used to avoid recursively entering coroutines.
*/
bool qemu_coroutine_entered(Coroutine *co);
/**
* Provides a mutex that can be used to synchronise coroutines
@ -149,24 +68,6 @@ struct CoMutex {
Coroutine *holder;
};
/**
* Initialises a CoMutex. This must be called before any other operation is used
* on the CoMutex.
*/
void qemu_co_mutex_init(CoMutex *mutex);
/**
* Locks the mutex. If the lock cannot be taken immediately, control is
* transferred to the caller of the current coroutine.
*/
void coroutine_fn qemu_co_mutex_lock(CoMutex *mutex);
/**
* Unlocks the mutex and schedules the next coroutine that was waiting for this
* lock to be run.
*/
void coroutine_fn qemu_co_mutex_unlock(CoMutex *mutex);
/**
* Assert that the current coroutine holds @mutex.
*/

2
include/qemu/lockable.h
View file

@ -13,7 +13,7 @@
#ifndef QEMU_LOCKABLE_H
#define QEMU_LOCKABLE_H
#include "qemu/coroutine.h"
#include "qemu/coroutine-core.h"
#include "qemu/thread.h"
typedef void QemuLockUnlockFunc(void *);

16
include/qemu/osdep.h
View file

@ -157,6 +157,22 @@ extern "C" {
#include "qemu/typedefs.h"
/**
* Mark a function that executes in coroutine context
*
* Functions that execute in coroutine context cannot be called directly from
* normal functions. In the future it would be nice to enable compiler or
* static checker support for catching such errors. This annotation might make
* it possible and in the meantime it serves as documentation.
*
* For example:
*
* static void coroutine_fn foo(void) {
* ....
* }
*/
#define coroutine_fn
/*
* For mingw, as of v6.0.0, the function implementing the assert macro is
* not marked as noreturn, so the compiler cannot delete code following an

2
include/qemu/progress_meter.h
View file

@ -27,7 +27,7 @@
#ifndef QEMU_PROGRESS_METER_H
#define QEMU_PROGRESS_METER_H
#include "qemu/lockable.h"
#include "qemu/thread.h"
typedef struct ProgressMeter {
/**

1
include/qemu/typedefs.h
View file

@ -38,7 +38,6 @@ typedef struct BusState BusState;
typedef struct Chardev Chardev;
typedef struct Clock Clock;
typedef struct CompatProperty CompatProperty;
typedef struct CoMutex CoMutex;
typedef struct ConfidentialGuestSupport ConfidentialGuestSupport;
typedef struct CPUAddressSpace CPUAddressSpace;
typedef struct CPUArchState CPUArchState;

1
include/scsi/pr-manager.h
View file

@ -5,7 +5,6 @@
#include "qapi/visitor.h"
#include "qom/object_interfaces.h"
#include "block/aio.h"
#include "qemu/coroutine.h"
#define TYPE_PR_MANAGER "pr-manager"

1
include/sysemu/block-backend-io.h
View file

@ -14,6 +14,7 @@
#define BLOCK_BACKEND_IO_H
#include "block-backend-common.h"
#include "block/accounting.h"
/*
* I/O API functions. These functions are thread-safe.