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target/riscv: rvv: Apply vext_check_input_eew to OPIVI/OPIVX/OPFVF(vext_check_ss) instructions

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Handle the overlap of source registers with different EEWs.

Co-authored-by: Anton Blanchard <antonb@tenstorrent.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Signed-off-by: Max Chou <max.chou@sifive.com>
Message-ID: <20250408103938.3623486-5-max.chou@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Cc: qemu-stable@nongnu.org
This commit is contained in:
Max Chou 2025-04-08 18:39:32 +08:00 • committed by Alistair Francis
parent 629c2a8dd7
commit fbeaf35838
1 changed files with 2 additions and 1 deletions
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3
target/riscv/insn_trans/trans_rvv.c.inc
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@ -412,7 +412,8 @@ static bool vext_check_ss(DisasContext *s, int vd, int vs, int vm)
{ {
return require_vm(vm, vd) && return require_vm(vm, vd) &&
require_align(vd, s->lmul) && require_align(vd, s->lmul) &&
require_align(vs, s->lmul); require_align(vs, s->lmul) &&
vext_check_input_eew(s, vs, s->sew, -1, s->sew, vm);
} }
/* /*