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RISC-V: Use riscv prefix consistently on cpu helpers

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* Add riscv prefix to raise_exception function
* Add riscv prefix to CSR read/write functions
* Add riscv prefix to signal handler function
* Add riscv prefix to get fflags function
* Remove redundant declaration of riscv_cpu_init
  and rename cpu_riscv_init to riscv_cpu_init
* rename riscv_set_mode to riscv_cpu_set_mode

Signed-off-by: Michael Clark <mjc@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
This commit is contained in:
Michael Clark 2019-01-14 23:58:23 +00:00 • committed by Palmer Dabbelt
parent 7f2b5ff125
commit fb73883964
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GPG key ID: EF4CA1502CCBAB41
6 changed files with 38 additions and 39 deletions
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10
target/riscv/cpu_helper.c
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@ -93,7 +93,7 @@ uint32_t riscv_cpu_update_mip(RISCVCPU *cpu, uint32_t mask, uint32_t value)
return old;
}
void riscv_set_mode(CPURISCVState *env, target_ulong newpriv)
void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv)
{
if (newpriv > PRV_M) {
g_assert_not_reached();
@ -366,7 +366,7 @@ void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
g_assert_not_reached();
}
env->badaddr = addr;
do_raise_exception_err(env, cs->exception_index, retaddr);
riscv_raise_exception(env, cs->exception_index, retaddr);
}
/* called by qemu's softmmu to fill the qemu tlb */
@ -378,7 +378,7 @@ void tlb_fill(CPUState *cs, target_ulong addr, int size,
if (ret == TRANSLATE_FAIL) {
RISCVCPU *cpu = RISCV_CPU(cs);
CPURISCVState *env = &cpu->env;
do_raise_exception_err(env, cs->exception_index, retaddr);
riscv_raise_exception(env, cs->exception_index, retaddr);
}
}
@ -530,7 +530,7 @@ void riscv_cpu_do_interrupt(CPUState *cs)
s = set_field(s, MSTATUS_SPP, env->priv);
s = set_field(s, MSTATUS_SIE, 0);
env->mstatus = s;
riscv_set_mode(env, PRV_S);
riscv_cpu_set_mode(env, PRV_S);
} else {
/* No need to check MTVEC for misaligned - lower 2 bits cannot be set */
env->pc = env->mtvec;
@ -555,7 +555,7 @@ void riscv_cpu_do_interrupt(CPUState *cs)
s = set_field(s, MSTATUS_MPP, env->priv);
s = set_field(s, MSTATUS_MIE, 0);
env->mstatus = s;
riscv_set_mode(env, PRV_M);
riscv_cpu_set_mode(env, PRV_M);
}
/* TODO yield load reservation */
#endif