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hw/arm/smmuv3: Implement MMIO write operations
Now we have relevant helpers for queue and irq management, let's implement MMIO write operations. Signed-off-by: Eric Auger <eric.auger@redhat.com> Signed-off-by: Prem Mallappa <prem.mallappa@broadcom.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1524665762-31355-8-git-send-email-eric.auger@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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3 changed files with 174 additions and 10 deletions
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@ -61,6 +61,8 @@ REG32(CR0, 0x20)
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FIELD(CR0, EVENTQEN, 2, 1)
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FIELD(CR0, CMDQEN, 3, 1)
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#define SMMU_CR0_RESERVED 0xFFFFFC20
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REG32(CR0ACK, 0x24)
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REG32(CR1, 0x28)
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REG32(CR2, 0x2c)
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@ -149,10 +151,6 @@ static inline bool smmuv3_gerror_irq_enabled(SMMUv3State *s)
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return FIELD_EX32(s->irq_ctrl, IRQ_CTRL, GERROR_IRQEN);
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}
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/* public until callers get introduced */
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void smmuv3_trigger_irq(SMMUv3State *s, SMMUIrq irq, uint32_t gerror_mask);
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void smmuv3_write_gerrorn(SMMUv3State *s, uint32_t gerrorn);
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/* Queue Handling */
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#define Q_BASE(q) ((q)->base & SMMU_BASE_ADDR_MASK)
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@ -314,6 +312,6 @@ enum { /* Command completion notification */
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addr; \
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})
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int smmuv3_cmdq_consume(SMMUv3State *s);
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#define SMMU_FEATURE_2LVL_STE (1 << 0)
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#endif
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