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tcg/riscv: Use SRAIW, SRLIW for {s}extract_i64

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Extracts which abut bit 32 may use 32-bit shifts.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson 2024-12-29 20:52:12 -08:00
parent 841e2c5257
commit fa65f13555
2 changed files with 19 additions and 21 deletions
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24
tcg/riscv/tcg-target-has.h
View file

@ -112,31 +112,21 @@
static inline bool
tcg_target_extract_valid(TCGType type, unsigned ofs, unsigned len)
{
if (ofs == 0) {
switch (len) {
case 16:
return cpuinfo & CPUINFO_ZBB;
case 32:
return (cpuinfo & CPUINFO_ZBA) && type == TCG_TYPE_I64;
}
if (type == TCG_TYPE_I64 && ofs + len == 32) {
/* ofs > 0 uses SRLIW; ofs == 0 uses add.uw. */
return ofs || (cpuinfo & CPUINFO_ZBA);
}
return false;
return (cpuinfo & CPUINFO_ZBB) && ofs == 0 && len == 16;
}
#define TCG_TARGET_extract_valid tcg_target_extract_valid
static inline bool
tcg_target_sextract_valid(TCGType type, unsigned ofs, unsigned len)
{
if (ofs == 0) {
switch (len) {
case 8:
case 16:
return cpuinfo & CPUINFO_ZBB;
case 32:
return type == TCG_TYPE_I64;
}
if (type == TCG_TYPE_I64 && ofs + len == 32) {
return true;
}
return false;
return (cpuinfo & CPUINFO_ZBB) && ofs == 0 && (len == 8 || len == 16);
}
#define TCG_TARGET_sextract_valid tcg_target_sextract_valid

16
tcg/riscv/tcg-target.c.inc
View file

@ -2344,8 +2344,12 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
break;
case INDEX_op_extract_i64:
if (a2 == 0 && args[3] == 32) {
tcg_out_ext32u(s, a0, a1);
if (a2 + args[3] == 32) {
if (a2 == 0) {
tcg_out_ext32u(s, a0, a1);
} else {
tcg_out_opc_imm(s, OPC_SRLIW, a0, a1, a2);
}
break;
}
/* FALLTHRU */
@ -2358,8 +2362,12 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
break;
case INDEX_op_sextract_i64:
if (a2 == 0 && args[3] == 32) {
tcg_out_ext32s(s, a0, a1);
if (a2 + args[3] == 32) {
if (a2 == 0) {
tcg_out_ext32s(s, a0, a1);
} else {
tcg_out_opc_imm(s, OPC_SRAIW, a0, a1, a2);
}
break;
}
/* FALLTHRU */