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target/arm: New helper function arm_v7m_mmu_idx_all()

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Add a new helper function which returns the MMU index to use
for v7M, where the caller specifies all of the security
state, privilege level and whether the execution priority
is negative, and reimplement the existing
arm_v7m_mmu_idx_for_secstate_and_priv() in terms of it.

We are going to need this for the lazy-FP-stacking code.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20190416125744.27770-21-peter.maydell@linaro.org
This commit is contained in:
Peter Maydell 2019-04-29 17:36:02 +01:00
parent 6000531e19
commit fa6252a988
2 changed files with 18 additions and 3 deletions
Download patch file Download diff file Expand all files Collapse all files

7
target/arm/cpu.h
View file

@ -2911,6 +2911,13 @@ static inline int arm_mmu_idx_to_el(ARMMMUIdx mmu_idx)
} }
} }
/*
* Return the MMU index for a v7M CPU with all relevant information
* manually specified.
*/
ARMMMUIdx arm_v7m_mmu_idx_all(CPUARMState *env,
bool secstate, bool priv, bool negpri);
/* Return the MMU index for a v7M CPU in the specified security and /* Return the MMU index for a v7M CPU in the specified security and
* privilege state. * privilege state.
*/ */

14
target/arm/helper.c
View file

@ -13230,8 +13230,8 @@ int fp_exception_el(CPUARMState *env, int cur_el)
return 0; return 0;
} }
ARMMMUIdx arm_v7m_mmu_idx_for_secstate_and_priv(CPUARMState *env, ARMMMUIdx arm_v7m_mmu_idx_all(CPUARMState *env,
bool secstate, bool priv) bool secstate, bool priv, bool negpri)
{ {
ARMMMUIdx mmu_idx = ARM_MMU_IDX_M; ARMMMUIdx mmu_idx = ARM_MMU_IDX_M;
@ -13239,7 +13239,7 @@ ARMMMUIdx arm_v7m_mmu_idx_for_secstate_and_priv(CPUARMState *env,
mmu_idx |= ARM_MMU_IDX_M_PRIV; mmu_idx |= ARM_MMU_IDX_M_PRIV;
} }
if (armv7m_nvic_neg_prio_requested(env->nvic, secstate)) { if (negpri) {
mmu_idx |= ARM_MMU_IDX_M_NEGPRI; mmu_idx |= ARM_MMU_IDX_M_NEGPRI;
} }
@ -13250,6 +13250,14 @@ ARMMMUIdx arm_v7m_mmu_idx_for_secstate_and_priv(CPUARMState *env,
return mmu_idx; return mmu_idx;
} }
ARMMMUIdx arm_v7m_mmu_idx_for_secstate_and_priv(CPUARMState *env,
bool secstate, bool priv)
{
bool negpri = armv7m_nvic_neg_prio_requested(env->nvic, secstate);
return arm_v7m_mmu_idx_all(env, secstate, priv, negpri);
}
/* Return the MMU index for a v7M CPU in the specified security state */ /* Return the MMU index for a v7M CPU in the specified security state */
ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate) ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate)
{ {