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aspeed/scu: Add AST1030 support

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Per ast1030_v07.pdf, AST1030 SOC doesn't have SCU300, the pclk divider
selection is defined in SCU310[11:8].
Add a get_apb_freq function and a class init handler for ast1030.

Signed-off-by: Troy Lee <troy_lee@aspeedtech.com>
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
Signed-off-by: Steven Lee <steven_lee@aspeedtech.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20220401083850.15266-7-jamin_lin@aspeedtech.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
This commit is contained in:
Steven Lee 2022-05-02 17:03:03 +02:00 • committed by Cédric Le Goater
parent c5b89a4f47
commit fa541a60dd
2 changed files with 88 additions and 0 deletions
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25
include/hw/misc/aspeed_scu.h
View file

@ -19,6 +19,7 @@ OBJECT_DECLARE_TYPE(AspeedSCUState, AspeedSCUClass, ASPEED_SCU)
#define TYPE_ASPEED_2400_SCU TYPE_ASPEED_SCU "-ast2400"
#define TYPE_ASPEED_2500_SCU TYPE_ASPEED_SCU "-ast2500"
#define TYPE_ASPEED_2600_SCU TYPE_ASPEED_SCU "-ast2600"
#define TYPE_ASPEED_1030_SCU TYPE_ASPEED_SCU "-ast1030"
#define ASPEED_SCU_NR_REGS (0x1A8 >> 2)
#define ASPEED_AST2600_SCU_NR_REGS (0xE20 >> 2)
@ -45,6 +46,8 @@ struct AspeedSCUState {
#define AST2600_A1_SILICON_REV 0x05010303U
#define AST2600_A2_SILICON_REV 0x05020303U
#define AST2600_A3_SILICON_REV 0x05030303U
#define AST1030_A0_SILICON_REV 0x80000000U
#define AST1030_A1_SILICON_REV 0x80010000U
#define ASPEED_IS_AST2500(si_rev) ((((si_rev) >> 24) & 0xff) == 0x04)
@ -336,4 +339,26 @@ uint32_t aspeed_scu_get_apb_freq(AspeedSCUState *s);
#define SCU_AST2600_H_PLL_BYPASS_EN (0x1 << 24)
#define SCU_AST2600_H_PLL_OFF (0x1 << 23)
/*
* SCU310 Clock Selection Register Set 4 (for Aspeed AST1030 SOC)
*
* 31 I3C Clock Source selection
* 30:28 I3C clock divider selection
* 26:24 MAC AHB clock divider selection
* 22:20 RGMII 125MHz clock divider ration
* 19:16 RGMII 50MHz clock divider ration
* 15 LHCLK clock generation/output enable control
* 14:12 LHCLK divider selection
* 11:8 APB Bus PCLK divider selection
* 7 Select PECI clock source
* 6 Select UART debug port clock source
* 5 Select UART6 clock source
* 4 Select UART5 clock source
* 3 Select UART4 clock source
* 2 Select UART3 clock source
* 1 Select UART2 clock source
* 0 Select UART1 clock source
*/
#define SCU_AST1030_CLK_GET_PCLK_DIV(x) (((x) >> 8) & 0xf)
#endif /* ASPEED_SCU_H */