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ppc/xive: export the TIMA memory accessors

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The PowerNV machine can perform indirect loads and stores on the TIMA
on behalf of another CPU. Give the controller the possibility to call
the TIMA memory accessors with a XiveTCTX of its choice.

Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20190306085032.15744-4-clg@kaod.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
This commit is contained in:
Cédric Le Goater 2019-03-06 09:50:08 +01:00 • committed by David Gibson
parent 051e2973bf
commit f9b9db3860
2 changed files with 21 additions and 5 deletions
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23
hw/intc/xive.c
View file

@ -317,10 +317,9 @@ static const XiveTmOp *xive_tm_find_op(hwaddr offset, unsigned size, bool write)
/* /*
* TIMA MMIO handlers * TIMA MMIO handlers
*/ */
static void xive_tm_write(void *opaque, hwaddr offset, void xive_tctx_tm_write(XiveTCTX *tctx, hwaddr offset, uint64_t value,
uint64_t value, unsigned size) unsigned size)
{ {
XiveTCTX *tctx = xive_router_get_tctx(XIVE_ROUTER(opaque), current_cpu);
const XiveTmOp *xto; const XiveTmOp *xto;
/* /*
@ -356,9 +355,8 @@ static void xive_tm_write(void *opaque, hwaddr offset,
xive_tm_raw_write(tctx, offset, value, size); xive_tm_raw_write(tctx, offset, value, size);
} }
static uint64_t xive_tm_read(void *opaque, hwaddr offset, unsigned size) uint64_t xive_tctx_tm_read(XiveTCTX *tctx, hwaddr offset, unsigned size)
{ {
XiveTCTX *tctx = xive_router_get_tctx(XIVE_ROUTER(opaque), current_cpu);
const XiveTmOp *xto; const XiveTmOp *xto;
/* /*
@ -392,6 +390,21 @@ static uint64_t xive_tm_read(void *opaque, hwaddr offset, unsigned size)
return xive_tm_raw_read(tctx, offset, size); return xive_tm_raw_read(tctx, offset, size);
} }
static void xive_tm_write(void *opaque, hwaddr offset,
uint64_t value, unsigned size)
{
XiveTCTX *tctx = xive_router_get_tctx(XIVE_ROUTER(opaque), current_cpu);
xive_tctx_tm_write(tctx, offset, value, size);
}
static uint64_t xive_tm_read(void *opaque, hwaddr offset, unsigned size)
{
XiveTCTX *tctx = xive_router_get_tctx(XIVE_ROUTER(opaque), current_cpu);
return xive_tctx_tm_read(tctx, offset, size);
}
const MemoryRegionOps xive_tm_ops = { const MemoryRegionOps xive_tm_ops = {
.read = xive_tm_read, .read = xive_tm_read,
.write = xive_tm_write, .write = xive_tm_write,

3
include/hw/ppc/xive.h
View file

@ -410,6 +410,9 @@ void xive_end_queue_pic_print_info(XiveEND *end, uint32_t width, Monitor *mon);
#define XIVE_TM_USER_PAGE 0x3 #define XIVE_TM_USER_PAGE 0x3
extern const MemoryRegionOps xive_tm_ops; extern const MemoryRegionOps xive_tm_ops;
void xive_tctx_tm_write(XiveTCTX *tctx, hwaddr offset, uint64_t value,
unsigned size);
uint64_t xive_tctx_tm_read(XiveTCTX *tctx, hwaddr offset, unsigned size);
void xive_tctx_pic_print_info(XiveTCTX *tctx, Monitor *mon); void xive_tctx_pic_print_info(XiveTCTX *tctx, Monitor *mon);
Object *xive_tctx_create(Object *cpu, XiveRouter *xrtr, Error **errp); Object *xive_tctx_create(Object *cpu, XiveRouter *xrtr, Error **errp);