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tcg: Replace IMPLVEC with TCG_OPF_VECTOR
This is now a direct replacement. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson
parent
76187b4f57
commit
f9af66f6dc
6 changed files with 68 additions and 71 deletions
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@ -221,66 +221,63 @@ DEF(qemu_st_a64_i128, 0, 3, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
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/* Host vector support. */
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#define IMPLVEC TCG_OPF_VECTOR
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DEF(mov_vec, 1, 1, 0, TCG_OPF_VECTOR | TCG_OPF_NOT_PRESENT)
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DEF(dup_vec, 1, 1, 0, IMPLVEC)
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DEF(dup2_vec, 1, 2, 0, IMPLVEC)
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DEF(dup_vec, 1, 1, 0, TCG_OPF_VECTOR)
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DEF(dup2_vec, 1, 2, 0, TCG_OPF_VECTOR)
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DEF(ld_vec, 1, 1, 1, IMPLVEC)
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DEF(st_vec, 0, 2, 1, IMPLVEC)
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DEF(dupm_vec, 1, 1, 1, IMPLVEC)
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DEF(ld_vec, 1, 1, 1, TCG_OPF_VECTOR)
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DEF(st_vec, 0, 2, 1, TCG_OPF_VECTOR)
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DEF(dupm_vec, 1, 1, 1, TCG_OPF_VECTOR)
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DEF(add_vec, 1, 2, 0, IMPLVEC)
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DEF(sub_vec, 1, 2, 0, IMPLVEC)
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DEF(mul_vec, 1, 2, 0, IMPLVEC)
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DEF(neg_vec, 1, 1, 0, IMPLVEC)
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DEF(abs_vec, 1, 1, 0, IMPLVEC)
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DEF(ssadd_vec, 1, 2, 0, IMPLVEC)
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DEF(usadd_vec, 1, 2, 0, IMPLVEC)
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DEF(sssub_vec, 1, 2, 0, IMPLVEC)
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DEF(ussub_vec, 1, 2, 0, IMPLVEC)
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DEF(smin_vec, 1, 2, 0, IMPLVEC)
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DEF(umin_vec, 1, 2, 0, IMPLVEC)
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DEF(smax_vec, 1, 2, 0, IMPLVEC)
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DEF(umax_vec, 1, 2, 0, IMPLVEC)
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DEF(add_vec, 1, 2, 0, TCG_OPF_VECTOR)
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DEF(sub_vec, 1, 2, 0, TCG_OPF_VECTOR)
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DEF(mul_vec, 1, 2, 0, TCG_OPF_VECTOR)
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DEF(neg_vec, 1, 1, 0, TCG_OPF_VECTOR)
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DEF(abs_vec, 1, 1, 0, TCG_OPF_VECTOR)
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DEF(ssadd_vec, 1, 2, 0, TCG_OPF_VECTOR)
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DEF(usadd_vec, 1, 2, 0, TCG_OPF_VECTOR)
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DEF(sssub_vec, 1, 2, 0, TCG_OPF_VECTOR)
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DEF(ussub_vec, 1, 2, 0, TCG_OPF_VECTOR)
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DEF(smin_vec, 1, 2, 0, TCG_OPF_VECTOR)
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DEF(umin_vec, 1, 2, 0, TCG_OPF_VECTOR)
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DEF(smax_vec, 1, 2, 0, TCG_OPF_VECTOR)
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DEF(umax_vec, 1, 2, 0, TCG_OPF_VECTOR)
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DEF(and_vec, 1, 2, 0, IMPLVEC)
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DEF(or_vec, 1, 2, 0, IMPLVEC)
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DEF(xor_vec, 1, 2, 0, IMPLVEC)
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DEF(andc_vec, 1, 2, 0, IMPLVEC)
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DEF(orc_vec, 1, 2, 0, IMPLVEC)
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DEF(nand_vec, 1, 2, 0, IMPLVEC)
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DEF(nor_vec, 1, 2, 0, IMPLVEC)
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DEF(eqv_vec, 1, 2, 0, IMPLVEC)
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DEF(not_vec, 1, 1, 0, IMPLVEC)
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DEF(and_vec, 1, 2, 0, TCG_OPF_VECTOR)
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DEF(or_vec, 1, 2, 0, TCG_OPF_VECTOR)
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DEF(xor_vec, 1, 2, 0, TCG_OPF_VECTOR)
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DEF(andc_vec, 1, 2, 0, TCG_OPF_VECTOR)
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DEF(orc_vec, 1, 2, 0, TCG_OPF_VECTOR)
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DEF(nand_vec, 1, 2, 0, TCG_OPF_VECTOR)
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DEF(nor_vec, 1, 2, 0, TCG_OPF_VECTOR)
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DEF(eqv_vec, 1, 2, 0, TCG_OPF_VECTOR)
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DEF(not_vec, 1, 1, 0, TCG_OPF_VECTOR)
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DEF(shli_vec, 1, 1, 1, IMPLVEC)
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DEF(shri_vec, 1, 1, 1, IMPLVEC)
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DEF(sari_vec, 1, 1, 1, IMPLVEC)
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DEF(rotli_vec, 1, 1, 1, IMPLVEC)
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DEF(shli_vec, 1, 1, 1, TCG_OPF_VECTOR)
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DEF(shri_vec, 1, 1, 1, TCG_OPF_VECTOR)
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DEF(sari_vec, 1, 1, 1, TCG_OPF_VECTOR)
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DEF(rotli_vec, 1, 1, 1, TCG_OPF_VECTOR)
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DEF(shls_vec, 1, 2, 0, IMPLVEC)
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DEF(shrs_vec, 1, 2, 0, IMPLVEC)
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DEF(sars_vec, 1, 2, 0, IMPLVEC)
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DEF(rotls_vec, 1, 2, 0, IMPLVEC)
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DEF(shls_vec, 1, 2, 0, TCG_OPF_VECTOR)
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DEF(shrs_vec, 1, 2, 0, TCG_OPF_VECTOR)
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DEF(sars_vec, 1, 2, 0, TCG_OPF_VECTOR)
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DEF(rotls_vec, 1, 2, 0, TCG_OPF_VECTOR)
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DEF(shlv_vec, 1, 2, 0, IMPLVEC)
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DEF(shrv_vec, 1, 2, 0, IMPLVEC)
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DEF(sarv_vec, 1, 2, 0, IMPLVEC)
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DEF(rotlv_vec, 1, 2, 0, IMPLVEC)
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DEF(rotrv_vec, 1, 2, 0, IMPLVEC)
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DEF(shlv_vec, 1, 2, 0, TCG_OPF_VECTOR)
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DEF(shrv_vec, 1, 2, 0, TCG_OPF_VECTOR)
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DEF(sarv_vec, 1, 2, 0, TCG_OPF_VECTOR)
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DEF(rotlv_vec, 1, 2, 0, TCG_OPF_VECTOR)
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DEF(rotrv_vec, 1, 2, 0, TCG_OPF_VECTOR)
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DEF(cmp_vec, 1, 2, 1, IMPLVEC)
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DEF(cmp_vec, 1, 2, 1, TCG_OPF_VECTOR)
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DEF(bitsel_vec, 1, 3, 0, IMPLVEC)
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DEF(cmpsel_vec, 1, 4, 1, IMPLVEC)
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DEF(bitsel_vec, 1, 3, 0, TCG_OPF_VECTOR)
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DEF(cmpsel_vec, 1, 4, 1, TCG_OPF_VECTOR)
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DEF(last_generic, 0, 0, 0, TCG_OPF_NOT_PRESENT)
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#include "tcg-target-opc.h.inc"
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#undef DATA64_ARGS
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#undef IMPLVEC
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#undef DEF
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@ -11,5 +11,5 @@
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* consider these to be UNSPEC with names.
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*/
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DEF(aa64_sshl_vec, 1, 2, 0, IMPLVEC)
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DEF(aa64_sli_vec, 1, 2, 1, IMPLVEC)
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DEF(aa64_sshl_vec, 1, 2, 0, TCG_OPF_VECTOR)
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DEF(aa64_sli_vec, 1, 2, 1, TCG_OPF_VECTOR)
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@ -11,6 +11,6 @@
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* consider these to be UNSPEC with names.
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*/
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DEF(arm_sli_vec, 1, 2, 1, IMPLVEC)
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DEF(arm_sshl_vec, 1, 2, 0, IMPLVEC)
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DEF(arm_ushl_vec, 1, 2, 0, IMPLVEC)
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DEF(arm_sli_vec, 1, 2, 1, TCG_OPF_VECTOR)
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DEF(arm_sshl_vec, 1, 2, 0, TCG_OPF_VECTOR)
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DEF(arm_ushl_vec, 1, 2, 0, TCG_OPF_VECTOR)
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@ -24,14 +24,14 @@
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* consider these to be UNSPEC with names.
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*/
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DEF(x86_shufps_vec, 1, 2, 1, IMPLVEC)
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DEF(x86_blend_vec, 1, 2, 1, IMPLVEC)
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DEF(x86_packss_vec, 1, 2, 0, IMPLVEC)
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DEF(x86_packus_vec, 1, 2, 0, IMPLVEC)
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DEF(x86_psrldq_vec, 1, 1, 1, IMPLVEC)
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DEF(x86_vperm2i128_vec, 1, 2, 1, IMPLVEC)
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DEF(x86_punpckl_vec, 1, 2, 0, IMPLVEC)
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DEF(x86_punpckh_vec, 1, 2, 0, IMPLVEC)
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DEF(x86_vpshldi_vec, 1, 2, 1, IMPLVEC)
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DEF(x86_vpshldv_vec, 1, 3, 0, IMPLVEC)
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DEF(x86_vpshrdv_vec, 1, 3, 0, IMPLVEC)
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DEF(x86_shufps_vec, 1, 2, 1, TCG_OPF_VECTOR)
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DEF(x86_blend_vec, 1, 2, 1, TCG_OPF_VECTOR)
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DEF(x86_packss_vec, 1, 2, 0, TCG_OPF_VECTOR)
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DEF(x86_packus_vec, 1, 2, 0, TCG_OPF_VECTOR)
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DEF(x86_psrldq_vec, 1, 1, 1, TCG_OPF_VECTOR)
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DEF(x86_vperm2i128_vec, 1, 2, 1, TCG_OPF_VECTOR)
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DEF(x86_punpckl_vec, 1, 2, 0, TCG_OPF_VECTOR)
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DEF(x86_punpckh_vec, 1, 2, 0, TCG_OPF_VECTOR)
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DEF(x86_vpshldi_vec, 1, 2, 1, TCG_OPF_VECTOR)
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DEF(x86_vpshldv_vec, 1, 3, 0, TCG_OPF_VECTOR)
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DEF(x86_vpshrdv_vec, 1, 3, 0, TCG_OPF_VECTOR)
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@ -24,9 +24,9 @@
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* consider these to be UNSPEC with names.
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*/
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DEF(ppc_mrgh_vec, 1, 2, 0, IMPLVEC)
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DEF(ppc_mrgl_vec, 1, 2, 0, IMPLVEC)
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DEF(ppc_msum_vec, 1, 3, 0, IMPLVEC)
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DEF(ppc_muleu_vec, 1, 2, 0, IMPLVEC)
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DEF(ppc_mulou_vec, 1, 2, 0, IMPLVEC)
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DEF(ppc_pkum_vec, 1, 2, 0, IMPLVEC)
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DEF(ppc_mrgh_vec, 1, 2, 0, TCG_OPF_VECTOR)
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DEF(ppc_mrgl_vec, 1, 2, 0, TCG_OPF_VECTOR)
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DEF(ppc_msum_vec, 1, 3, 0, TCG_OPF_VECTOR)
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DEF(ppc_muleu_vec, 1, 2, 0, TCG_OPF_VECTOR)
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DEF(ppc_mulou_vec, 1, 2, 0, TCG_OPF_VECTOR)
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DEF(ppc_pkum_vec, 1, 2, 0, TCG_OPF_VECTOR)
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@ -10,6 +10,6 @@
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* emitted by tcg_expand_vec_op. For those familiar with GCC internals,
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* consider these to be UNSPEC with names.
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*/
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DEF(s390_vuph_vec, 1, 1, 0, IMPLVEC)
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DEF(s390_vupl_vec, 1, 1, 0, IMPLVEC)
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DEF(s390_vpks_vec, 1, 2, 0, IMPLVEC)
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DEF(s390_vuph_vec, 1, 1, 0, TCG_OPF_VECTOR)
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DEF(s390_vupl_vec, 1, 1, 0, TCG_OPF_VECTOR)
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DEF(s390_vpks_vec, 1, 2, 0, TCG_OPF_VECTOR)
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