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pc: acpi: q35: move PCI0._OSC() method into SSDT

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Signed-off-by: Igor Mammedov <imammedo@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
This commit is contained in:
Igor Mammedov 2015-12-28 18:02:54 +01:00 • committed by Michael S. Tsirkin
parent e9fce79861
commit f97a88a85e
2 changed files with 56 additions and 57 deletions
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56
hw/i386/acpi-build.c
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@ -1896,6 +1896,54 @@ static void build_piix4_pci_hotplug(Aml *table)
aml_append(table, scope);
}
static Aml *build_q35_osc_method(void)
{
Aml *if_ctx;
Aml *if_ctx2;
Aml *else_ctx;
Aml *method;
Aml *a_cwd1 = aml_name("CDW1");
Aml *a_ctrl = aml_name("CTRL");
method = aml_method("_OSC", 4, AML_NOTSERIALIZED);
aml_append(method, aml_create_dword_field(aml_arg(3), aml_int(0), "CDW1"));
if_ctx = aml_if(aml_equal(
aml_arg(0), aml_touuid("33DB4D5B-1FF7-401C-9657-7441C03DD766")));
aml_append(if_ctx, aml_create_dword_field(aml_arg(3), aml_int(4), "CDW2"));
aml_append(if_ctx, aml_create_dword_field(aml_arg(3), aml_int(8), "CDW3"));
aml_append(if_ctx, aml_store(aml_name("CDW2"), aml_name("SUPP")));
aml_append(if_ctx, aml_store(aml_name("CDW3"), a_ctrl));
/*
* Always allow native PME, AER (no dependencies)
* Never allow SHPC (no SHPC controller in this system)
*/
aml_append(if_ctx, aml_and(a_ctrl, aml_int(0x1D), a_ctrl));
if_ctx2 = aml_if(aml_lnot(aml_equal(aml_arg(1), aml_int(1))));
/* Unknown revision */
aml_append(if_ctx2, aml_or(a_cwd1, aml_int(0x08), a_cwd1));
aml_append(if_ctx, if_ctx2);
if_ctx2 = aml_if(aml_lnot(aml_equal(aml_name("CDW3"), a_ctrl)));
/* Capabilities bits were masked */
aml_append(if_ctx2, aml_or(a_cwd1, aml_int(0x10), a_cwd1));
aml_append(if_ctx, if_ctx2);
/* Update DWORD3 in the buffer */
aml_append(if_ctx, aml_store(a_ctrl, aml_name("CDW3")));
aml_append(method, if_ctx);
else_ctx = aml_else();
/* Unrecognized UUID */
aml_append(else_ctx, aml_or(a_cwd1, aml_int(4), a_cwd1));
aml_append(method, else_ctx);
aml_append(method, aml_return(aml_arg(3)));
return method;
}
static void
build_ssdt(GArray *table_data, GArray *linker,
@ -1934,6 +1982,14 @@ build_ssdt(GArray *table_data, GArray *linker,
build_piix4_pci_hotplug(ssdt);
build_piix4_pci0_int(ssdt);
} else {
sb_scope = aml_scope("_SB");
scope = aml_scope("PCI0");
aml_append(scope, aml_name_decl("SUPP", aml_int(0)));
aml_append(scope, aml_name_decl("CTRL", aml_int(0)));
aml_append(scope, build_q35_osc_method());
aml_append(sb_scope, scope);
aml_append(ssdt, sb_scope);
build_hpet_aml(ssdt);
build_q35_isa_bridge(ssdt);
build_isa_devices_aml(ssdt);