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target/i386: reimplement 0x0f 0x28-0x2f, add AVX

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Here the code is a bit uglier due to the truncation and extension
of registers to and from 32-bit.  There is also a mistake in the
manual with respect to the size of the memory operand of CVTPS2PI
and CVTTPS2PI, reported by Ricky Zhou.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
This commit is contained in:
Paolo Bonzini 2022-09-06 18:44:02 +02:00
parent 7170a17ec3
commit f8d19eec0d
3 changed files with 185 additions and 0 deletions
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56
target/i386/tcg/decode-new.c.inc
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@ -672,6 +672,53 @@ static void decode_0F16(DisasContext *s, CPUX86State *env, X86OpEntry *entry, ui
}
}
static void decode_0F2A(DisasContext *s, CPUX86State *env, X86OpEntry *entry, uint8_t *b)
{
static const X86OpEntry opcodes_0F2A[4] = {
X86_OP_ENTRY3(CVTPI2Px, V,x, None,None, Q,q),
X86_OP_ENTRY3(CVTPI2Px, V,x, None,None, Q,q),
X86_OP_ENTRY3(VCVTSI2Sx, V,x, H,x, E,y, vex3),
X86_OP_ENTRY3(VCVTSI2Sx, V,x, H,x, E,y, vex3),
};
*entry = *decode_by_prefix(s, opcodes_0F2A);
}
static void decode_0F2B(DisasContext *s, CPUX86State *env, X86OpEntry *entry, uint8_t *b)
{
static const X86OpEntry opcodes_0F2B[4] = {
X86_OP_ENTRY3(MOVDQ, M,x, None,None, V,x, vex4), /* MOVNTPS */
X86_OP_ENTRY3(MOVDQ, M,x, None,None, V,x, vex4), /* MOVNTPD */
X86_OP_ENTRY3(VMOVSS_st, M,ss, None,None, V,x, vex4 cpuid(SSE4A)), /* MOVNTSS */
X86_OP_ENTRY3(VMOVLPx_st, M,sd, None,None, V,x, vex4 cpuid(SSE4A)), /* MOVNTSD */
};
*entry = *decode_by_prefix(s, opcodes_0F2B);
}
static void decode_0F2C(DisasContext *s, CPUX86State *env, X86OpEntry *entry, uint8_t *b)
{
static const X86OpEntry opcodes_0F2C[4] = {
/* Listed as ps/pd in the manual, but CVTTPS2PI only reads 64-bit. */
X86_OP_ENTRY3(CVTTPx2PI, P,q, None,None, W,q),
X86_OP_ENTRY3(CVTTPx2PI, P,q, None,None, W,dq),
X86_OP_ENTRY3(VCVTTSx2SI, G,y, None,None, W,ss, vex3),
X86_OP_ENTRY3(VCVTTSx2SI, G,y, None,None, W,sd, vex3),
};
*entry = *decode_by_prefix(s, opcodes_0F2C);
}
static void decode_0F2D(DisasContext *s, CPUX86State *env, X86OpEntry *entry, uint8_t *b)
{
static const X86OpEntry opcodes_0F2D[4] = {
/* Listed as ps/pd in the manual, but CVTPS2PI only reads 64-bit. */
X86_OP_ENTRY3(CVTPx2PI, P,q, None,None, W,q),
X86_OP_ENTRY3(CVTPx2PI, P,q, None,None, W,dq),
X86_OP_ENTRY3(VCVTSx2SI, G,y, None,None, W,ss, vex3),
X86_OP_ENTRY3(VCVTSx2SI, G,y, None,None, W,sd, vex3),
};
*entry = *decode_by_prefix(s, opcodes_0F2D);
}
static void decode_sse_unary(DisasContext *s, CPUX86State *env, X86OpEntry *entry, uint8_t *b)
{
if (!(s->prefix & (PREFIX_REPZ | PREFIX_REPNZ))) {
@ -746,6 +793,15 @@ static const X86OpEntry opcodes_0F[256] = {
[0x76] = X86_OP_ENTRY3(PCMPEQD, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66),
[0x77] = X86_OP_GROUP0(0F77),
[0x28] = X86_OP_ENTRY3(MOVDQ, V,x, None,None, W,x, vex1 p_00_66), /* MOVAPS */
[0x29] = X86_OP_ENTRY3(MOVDQ, W,x, None,None, V,x, vex1 p_00_66), /* MOVAPS */
[0x2A] = X86_OP_GROUP0(0F2A),
[0x2B] = X86_OP_GROUP0(0F2B),
[0x2C] = X86_OP_GROUP0(0F2C),
[0x2D] = X86_OP_GROUP0(0F2D),
[0x2E] = X86_OP_ENTRY3(VUCOMI, None,None, V,x, W,x, vex4 p_00_66),
[0x2F] = X86_OP_ENTRY3(VCOMI, None,None, V,x, W,x, vex4 p_00_66),
[0x38] = X86_OP_GROUP0(0F38),
[0x3a] = X86_OP_GROUP0(0F3A),