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target/xtensa: implement FPU division and square root
This does not implement all opcodes related to div/sqrt as specified in the xtensa ISA, partly because the official specification is not complete and partly because precise implementation is unnecessarily complex. Instead instructions specific to the div/sqrt sequences are implemented differently, most of them as nops, but the results of div/sqrt sequences is preserved. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
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@ -231,6 +231,30 @@ float32 HELPER(msub_s)(CPUXtensaState *env, float32 a, float32 b, float32 c)
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&env->fp_status);
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}
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float64 HELPER(mkdadj_d)(CPUXtensaState *env, float64 a, float64 b)
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{
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set_use_first_nan(true, &env->fp_status);
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return float64_div(b, a, &env->fp_status);
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}
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float32 HELPER(mkdadj_s)(CPUXtensaState *env, float32 a, float32 b)
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{
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set_use_first_nan(env->config->use_first_nan, &env->fp_status);
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return float32_div(b, a, &env->fp_status);
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}
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float64 HELPER(mksadj_d)(CPUXtensaState *env, float64 v)
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{
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set_use_first_nan(true, &env->fp_status);
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return float64_sqrt(v, &env->fp_status);
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}
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float32 HELPER(mksadj_s)(CPUXtensaState *env, float32 v)
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{
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set_use_first_nan(env->config->use_first_nan, &env->fp_status);
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return float32_sqrt(v, &env->fp_status);
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}
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uint32_t HELPER(ftoi_d)(CPUXtensaState *env, float64 v,
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uint32_t rounding_mode, uint32_t scale)
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{
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