motorhead/qemu
1
0
Fork 0
mirror of https://github.com/Motorhead1991/qemu.git synced 2025-08-06 01:03:55 -06:00
Code Issues Projects Releases Packages Wiki Activity Actions

target/loongarch: Add LoongArch IOCSR instruction

Browse source 
This includes:
- IOCSR{RD/WR}.{B/H/W/D}

Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
Signed-off-by: Song Gao <gaosong@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220606124333.2060567-27-yangxiaojuan@loongson.cn>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Xiaojuan Yang 2022-06-06 20:43:16 +08:00 • committed by Richard Henderson
parent 5b1dedfe84
commit f84a2aacf5
8 changed files with 197 additions and 0 deletions
Download patch file Download diff file Expand all files Collapse all files

35
target/loongarch/insn_trans/trans_privileged.c.inc
View file

@ -262,3 +262,38 @@ static bool trans_csrxchg(DisasContext *ctx, arg_csrxchg *a)
tcg_temp_free(oldv);
return true;
}
static bool gen_iocsrrd(DisasContext *ctx, arg_rr *a,
void (*func)(TCGv, TCGv_ptr, TCGv))
{
TCGv dest = gpr_dst(ctx, a->rd, EXT_NONE);
TCGv src1 = gpr_src(ctx, a->rj, EXT_NONE);
if (check_plv(ctx)) {
return false;
}
func(dest, cpu_env, src1);
return true;
}
static bool gen_iocsrwr(DisasContext *ctx, arg_rr *a,
void (*func)(TCGv_ptr, TCGv, TCGv))
{
TCGv val = gpr_src(ctx, a->rd, EXT_NONE);
TCGv addr = gpr_src(ctx, a->rj, EXT_NONE);
if (check_plv(ctx)) {
return false;
}
func(cpu_env, addr, val);
return true;
}
TRANS(iocsrrd_b, gen_iocsrrd, gen_helper_iocsrrd_b)
TRANS(iocsrrd_h, gen_iocsrrd, gen_helper_iocsrrd_h)
TRANS(iocsrrd_w, gen_iocsrrd, gen_helper_iocsrrd_w)
TRANS(iocsrrd_d, gen_iocsrrd, gen_helper_iocsrrd_d)
TRANS(iocsrwr_b, gen_iocsrwr, gen_helper_iocsrwr_b)
TRANS(iocsrwr_h, gen_iocsrwr, gen_helper_iocsrwr_h)
TRANS(iocsrwr_w, gen_iocsrwr, gen_helper_iocsrwr_w)
TRANS(iocsrwr_d, gen_iocsrwr, gen_helper_iocsrwr_d)