motorhead/qemu
1
0
Fork 0
mirror of https://github.com/Motorhead1991/qemu.git synced 2025-08-17 23:22:12 -06:00
Code Issues Projects Releases Packages Wiki Activity Actions

sdhci: clean up includes

Browse source 
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Alistair Francis <alistair.francis@xilinx.com>
Message-id: 20180115182436.2066-2-f4bug@amsat.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Philippe Mathieu-Daudé 2018-01-16 13:28:15 +00:00 • committed by Peter Maydell
parent 8081796a75
commit f82a0f449b
3 changed files with 7 additions and 5 deletions
Download patch file Download diff file Expand all files Collapse all files

4
hw/sd/sdhci-internal.h
View file

@ -24,8 +24,6 @@
#ifndef SDHCI_INTERNAL_H #ifndef SDHCI_INTERNAL_H
#define SDHCI_INTERNAL_H #define SDHCI_INTERNAL_H
#include "hw/sd/sdhci.h"
/* R/W SDMA System Address register 0x0 */ /* R/W SDMA System Address register 0x0 */
#define SDHC_SYSAD 0x00 #define SDHC_SYSAD 0x00
@ -227,6 +225,4 @@ enum {
sdhc_gap_write = 2 /* SDHC stopped at block gap during write operation */ sdhc_gap_write = 2 /* SDHC stopped at block gap during write operation */
}; };
extern const VMStateDescription sdhci_vmstate;
#endif #endif

1
hw/sd/sdhci.c
View file

@ -29,6 +29,7 @@
#include "sysemu/dma.h" #include "sysemu/dma.h"
#include "qemu/timer.h" #include "qemu/timer.h"
#include "qemu/bitops.h" #include "qemu/bitops.h"
#include "hw/sd/sdhci.h"
#include "sdhci-internal.h" #include "sdhci-internal.h"
#include "qemu/log.h" #include "qemu/log.h"

7
include/hw/sd/sdhci.h
View file

@ -26,17 +26,19 @@
#define SDHCI_H #define SDHCI_H
#include "qemu-common.h" #include "qemu-common.h"
#include "hw/block/block.h"
#include "hw/pci/pci.h" #include "hw/pci/pci.h"
#include "hw/sysbus.h" #include "hw/sysbus.h"
#include "hw/sd/sd.h" #include "hw/sd/sd.h"
/* SD/MMC host controller state */ /* SD/MMC host controller state */
typedef struct SDHCIState { typedef struct SDHCIState {
/*< private >*/
union { union {
PCIDevice pcidev; PCIDevice pcidev;
SysBusDevice busdev; SysBusDevice busdev;
}; };
/*< public >*/
SDBus sdbus; SDBus sdbus;
MemoryRegion iomem; MemoryRegion iomem;
@ -46,6 +48,7 @@ typedef struct SDHCIState {
qemu_irq ro_cb; qemu_irq ro_cb;
qemu_irq irq; qemu_irq irq;
/* Registers cleared on reset */
uint32_t sdmasysad; /* SDMA System Address register */ uint32_t sdmasysad; /* SDMA System Address register */
uint16_t blksize; /* Host DMA Buff Boundary and Transfer BlkSize Reg */ uint16_t blksize; /* Host DMA Buff Boundary and Transfer BlkSize Reg */
uint16_t blkcnt; /* Blocks count for current transfer */ uint16_t blkcnt; /* Blocks count for current transfer */
@ -70,8 +73,10 @@ typedef struct SDHCIState {
uint16_t acmd12errsts; /* Auto CMD12 error status register */ uint16_t acmd12errsts; /* Auto CMD12 error status register */
uint64_t admasysaddr; /* ADMA System Address Register */ uint64_t admasysaddr; /* ADMA System Address Register */
/* Read-only registers */
uint32_t capareg; /* Capabilities Register */ uint32_t capareg; /* Capabilities Register */
uint32_t maxcurr; /* Maximum Current Capabilities Register */ uint32_t maxcurr; /* Maximum Current Capabilities Register */
uint8_t *fifo_buffer; /* SD host i/o FIFO buffer */ uint8_t *fifo_buffer; /* SD host i/o FIFO buffer */
uint32_t buf_maxsz; uint32_t buf_maxsz;
uint16_t data_count; /* current element in FIFO buffer */ uint16_t data_count; /* current element in FIFO buffer */