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target-mips: fix DSP loads with rd = 0

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When rd is 0, which still need to do the actually load to possibly
generate a TLB exception.

Reviewed-by: Eric Johnson <ericj@mips.com>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
This commit is contained in:
Aurelien Jarno 2013-01-01 18:02:22 +01:00
parent 321f211707
commit f7d2072e25
1 changed files with 0 additions and 5 deletions
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5
target-mips/translate.c
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@ -12657,11 +12657,6 @@ static void gen_mipsdsp_ld(CPUMIPSState *env, DisasContext *ctx, uint32_t opc,
const char *opn = "ldx";
TCGv t0;
if (rd == 0) {
MIPS_DEBUG("NOP");
return;
}
check_dsp(ctx);
t0 = tcg_temp_new();