mirror of
https://github.com/Motorhead1991/qemu.git
synced 2025-08-10 02:54:58 -06:00
target-arm queue:
* hw/arm/omap1: Remove unused omap_uwire_attach() method
* stm32f405: Add RCC device to stm32f405 SoC
* arm/gicv3: add missing casts
* hw/misc: Create STM32L4x5 SYSCFG clock
* hw/arm: Add SPI to Allwinner A10
* hw/intc/omap_intc: Remove now-unnecessary abstract base class
* hw/char/pl011: Use correct masks for IBRD and FBRD
* docs/devel: Convert txt files to rST
* Remove MAX111X, MAX7310, DSCM-1XXXX, pcmcia devices (used only
by now-removed omap/pxa2xx boards)
* vl.c: Remove pxa2xx-specific -portrait and -rotate options
* dma: Fix function names in documentation
* hw/arm/xilinx_zynq: Add various missing unimplemented devices
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Merge tag 'pull-target-arm-20241015-1' of https://git.linaro.org/people/pmaydell/qemu-arm into staging
target-arm queue:
* hw/arm/omap1: Remove unused omap_uwire_attach() method
* stm32f405: Add RCC device to stm32f405 SoC
* arm/gicv3: add missing casts
* hw/misc: Create STM32L4x5 SYSCFG clock
* hw/arm: Add SPI to Allwinner A10
* hw/intc/omap_intc: Remove now-unnecessary abstract base class
* hw/char/pl011: Use correct masks for IBRD and FBRD
* docs/devel: Convert txt files to rST
* Remove MAX111X, MAX7310, DSCM-1XXXX, pcmcia devices (used only
by now-removed omap/pxa2xx boards)
* vl.c: Remove pxa2xx-specific -portrait and -rotate options
* dma: Fix function names in documentation
* hw/arm/xilinx_zynq: Add various missing unimplemented devices
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# -----END PGP SIGNATURE-----
# gpg: Signature made Tue 15 Oct 2024 15:17:05 BST
# gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg: issuer "peter.maydell@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate]
# gpg: aka "Peter Maydell <pmaydell@gmail.com>" [ultimate]
# gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [ultimate]
# gpg: aka "Peter Maydell <peter@archaic.org.uk>" [ultimate]
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE
* tag 'pull-target-arm-20241015-1' of https://git.linaro.org/people/pmaydell/qemu-arm: (28 commits)
hw/arm/xilinx_zynq: Add various missing unimplemented devices
dma: Fix function names in documentation
vl.c: Remove pxa2xx-specific -portrait and -rotate options
hw/block: Remove ecc
hw: Remove PCMCIA subsystem
hw/ide: Remove DSCM-1XXXX microdrive device model
hw/gpio: Remove MAX7310 device
hw/adc: Remove MAX111X device
docs/devel/lockcnt: Include kernel-doc API documentation
include: Move QemuLockCnt APIs to their own header
docs/devel/rcu: Convert to rST format
docs/devel/multiple-iothreads: Convert to rST format
docs/devel/lockcnt: Convert to rST format
docs/devel/blkverify: Convert to rST format
docs/devel/blkdebug: Convert to rST format
hw/char/pl011: Use correct masks for IBRD and FBRD
hw/intc/omap_intc: Remove now-unnecessary abstract base class
hw/arm: Add SPI to Allwinner A10
hw/ssi: Allwinner A10 SPI emulation
tests/qtest: Check STM32L4x5 clock connections
...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell
commit
f774a67750
81 changed files with 1802 additions and 2048 deletions
42
tests/qtest/stm32l4x5.h
Normal file
42
tests/qtest/stm32l4x5.h
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@ -0,0 +1,42 @@
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/*
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* QTest testcase header for STM32L4X5 :
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* used for consolidating common objects in stm32l4x5_*-test.c
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*
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* Copyright (c) 2024 Arnaud Minier <arnaud.minier@telecom-paris.fr>
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* Copyright (c) 2024 Inès Varhol <ines.varhol@telecom-paris.fr>
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*
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* This work is licensed under the terms of the GNU GPL, version 2 or later.
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* See the COPYING file in the top-level directory.
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*/
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#include "libqtest.h"
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/* copied from clock.h */
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#define CLOCK_PERIOD_1SEC (1000000000llu << 32)
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#define CLOCK_PERIOD_FROM_HZ(hz) (((hz) != 0) ? CLOCK_PERIOD_1SEC / (hz) : 0u)
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/*
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* MSI (4 MHz) is used as system clock source after startup
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* from Reset.
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* AHB, APB1 and APB2 prescalers are set to 1 at reset.
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*/
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#define SYSCLK_PERIOD CLOCK_PERIOD_FROM_HZ(4000000)
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#define RCC_AHB2ENR 0x4002104C
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#define RCC_APB1ENR1 0x40021058
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#define RCC_APB1ENR2 0x4002105C
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#define RCC_APB2ENR 0x40021060
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static inline uint64_t get_clock_period(QTestState *qts, const char *path)
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{
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uint64_t clock_period = 0;
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QDict *r;
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r = qtest_qmp(qts, "{ 'execute': 'qom-get', 'arguments':"
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" { 'path': %s, 'property': 'qtest-clock-period'} }", path);
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g_assert_false(qdict_haskey(r, "error"));
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clock_period = qdict_get_int(r, "return");
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qobject_unref(r);
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return clock_period;
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}
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@ -10,6 +10,7 @@
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#include "qemu/osdep.h"
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#include "libqtest-single.h"
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#include "stm32l4x5.h"
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#define GPIO_BASE_ADDR 0x48000000
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#define GPIO_SIZE 0x400
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@ -505,6 +506,26 @@ static void test_bsrr_brr(const void *data)
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gpio_writel(gpio, ODR, reset(gpio, ODR));
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}
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static void test_clock_enable(void)
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{
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/*
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* For each GPIO, enable its clock in RCC
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* and check that its clock period changes to SYSCLK_PERIOD
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*/
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unsigned int gpio_id;
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for (uint32_t gpio = GPIO_A; gpio <= GPIO_H; gpio += GPIO_B - GPIO_A) {
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gpio_id = get_gpio_id(gpio);
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g_autofree char *path = g_strdup_printf("/machine/soc/gpio%c/clk",
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gpio_id + 'a');
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g_assert_cmpuint(get_clock_period(global_qtest, path), ==, 0);
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/* Enable the gpio clock */
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writel(RCC_AHB2ENR, readl(RCC_AHB2ENR) | (0x1 << gpio_id));
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g_assert_cmpuint(get_clock_period(global_qtest, path), ==,
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SYSCLK_PERIOD);
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}
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}
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int main(int argc, char **argv)
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{
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int ret;
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@ -556,6 +577,8 @@ int main(int argc, char **argv)
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qtest_add_data_func("stm32l4x5/gpio/test_bsrr_brr2",
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test_data(GPIO_D, 0),
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test_bsrr_brr);
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qtest_add_func("stm32l4x5/gpio/test_clock_enable",
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test_clock_enable);
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qtest_start("-machine b-l475e-iot01a");
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ret = g_test_run();
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@ -10,6 +10,7 @@
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#include "qemu/osdep.h"
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#include "libqtest-single.h"
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#include "stm32l4x5.h"
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#define SYSCFG_BASE_ADDR 0x40010000
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#define SYSCFG_MEMRMP 0x00
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@ -26,7 +27,9 @@
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#define INVALID_ADDR 0x2C
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/* SoC forwards GPIOs to SysCfg */
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#define SYSCFG "/machine/soc"
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#define SOC "/machine/soc"
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#define SYSCFG "/machine/soc/syscfg"
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#define SYSCFG_CLK "/machine/soc/syscfg/clk"
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#define EXTI "/machine/soc/exti"
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static void syscfg_writel(unsigned int offset, uint32_t value)
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@ -41,7 +44,7 @@ static uint32_t syscfg_readl(unsigned int offset)
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static void syscfg_set_irq(int num, int level)
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{
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qtest_set_irq_in(global_qtest, SYSCFG, NULL, num, level);
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qtest_set_irq_in(global_qtest, SOC, NULL, num, level);
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}
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static void system_reset(void)
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@ -301,6 +304,17 @@ static void test_irq_gpio_multiplexer(void)
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syscfg_writel(SYSCFG_EXTICR1, 0x00000000);
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}
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static void test_clock_enable(void)
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{
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g_assert_cmpuint(get_clock_period(global_qtest, SYSCFG_CLK), ==, 0);
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/* Enable SYSCFG clock */
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writel(RCC_APB2ENR, readl(RCC_APB2ENR) | (0x1 << 0));
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g_assert_cmpuint(get_clock_period(global_qtest, SYSCFG_CLK), ==,
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SYSCLK_PERIOD);
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}
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int main(int argc, char **argv)
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{
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int ret;
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@ -325,6 +339,8 @@ int main(int argc, char **argv)
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test_irq_pin_multiplexer);
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qtest_add_func("stm32l4x5/syscfg/test_irq_gpio_multiplexer",
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test_irq_gpio_multiplexer);
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qtest_add_func("stm32l4x5/syscfg/test_clock_enable",
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test_clock_enable);
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qtest_start("-machine b-l475e-iot01a");
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ret = g_test_run();
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@ -12,6 +12,7 @@
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#include "libqtest.h"
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#include "hw/misc/stm32l4x5_rcc_internals.h"
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#include "hw/registerfields.h"
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#include "stm32l4x5.h"
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#define RCC_BASE_ADDR 0x40021000
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/* Use USART 1 ADDR, assume the others work the same */
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@ -331,6 +332,32 @@ static void test_ack(void)
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qtest_quit(qts);
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}
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static void check_clock(QTestState *qts, const char *path, uint32_t rcc_reg,
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uint32_t reg_offset)
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{
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g_assert_cmpuint(get_clock_period(qts, path), ==, 0);
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qtest_writel(qts, rcc_reg, qtest_readl(qts, rcc_reg) | (0x1 << reg_offset));
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g_assert_cmpuint(get_clock_period(qts, path), ==, SYSCLK_PERIOD);
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}
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static void test_clock_enable(void)
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{
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/*
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* For each USART device, enable its clock in RCC
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* and check that its clock frequency is SYSCLK_PERIOD
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*/
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QTestState *qts = qtest_init("-M b-l475e-iot01a");
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check_clock(qts, "machine/soc/usart[0]/clk", RCC_APB2ENR, 14);
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check_clock(qts, "machine/soc/usart[1]/clk", RCC_APB1ENR1, 17);
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check_clock(qts, "machine/soc/usart[2]/clk", RCC_APB1ENR1, 18);
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check_clock(qts, "machine/soc/uart[0]/clk", RCC_APB1ENR1, 19);
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check_clock(qts, "machine/soc/uart[1]/clk", RCC_APB1ENR1, 20);
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check_clock(qts, "machine/soc/lpuart1/clk", RCC_APB1ENR2, 0);
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qtest_quit(qts);
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}
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int main(int argc, char **argv)
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{
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int ret;
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@ -344,6 +371,7 @@ int main(int argc, char **argv)
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qtest_add_func("stm32l4x5/usart/receive_str", test_receive_str);
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qtest_add_func("stm32l4x5/usart/send_str", test_send_str);
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qtest_add_func("stm32l4x5/usart/ack", test_ack);
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qtest_add_func("stm32l4x5/usart/clock_enable", test_clock_enable);
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ret = g_test_run();
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return ret;
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