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target/riscv: Add basic vmstate description of CPU

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Add basic CPU state description to the newly created machine.c

Signed-off-by: Yifei Jiang <jiangyifei@huawei.com>
Signed-off-by: Yipeng Yin <yinyipeng1@huawei.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20201026115530.304-3-jiangyifei@huawei.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Yifei Jiang 2020-10-26 19:55:26 +08:00 • committed by Alistair Francis
parent 284d697c74
commit f7697f0e62
4 changed files with 81 additions and 8 deletions
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3
target/riscv/meson.build
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@ -27,7 +27,8 @@ riscv_ss.add(files(
riscv_softmmu_ss = ss.source_set()
riscv_softmmu_ss.add(files(
'pmp.c',
'monitor.c'
'monitor.c',
'machine.c'
))
target_arch += {'riscv': riscv_ss}