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https://github.com/Motorhead1991/qemu.git
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tcg: Add qemu_ld_st_i32/64
Step two in the transition, adding the new ldst opcodes. Keep the old opcodes around until all backends support the new opcodes. Signed-off-by: Richard Henderson <rth@twiddle.net>
This commit is contained in:
Richard Henderson
parent
6c5f4ead64
commit
f713d6ad7b
14 changed files with 366 additions and 237 deletions
209
tcg/tcg.c
209
tcg/tcg.c
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@ -811,6 +811,188 @@ void tcg_gen_shifti_i64(TCGv_i64 ret, TCGv_i64 arg1,
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}
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#endif
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static inline TCGMemOp tcg_canonicalize_memop(TCGMemOp op, bool is64, bool st)
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{
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switch (op & MO_SIZE) {
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case MO_8:
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op &= ~MO_BSWAP;
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break;
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case MO_16:
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break;
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case MO_32:
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if (!is64) {
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op &= ~MO_SIGN;
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}
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break;
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case MO_64:
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if (!is64) {
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tcg_abort();
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}
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break;
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}
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if (st) {
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op &= ~MO_SIGN;
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}
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return op;
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}
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static const TCGOpcode old_ld_opc[8] = {
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[MO_UB] = INDEX_op_qemu_ld8u,
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[MO_SB] = INDEX_op_qemu_ld8s,
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[MO_UW] = INDEX_op_qemu_ld16u,
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[MO_SW] = INDEX_op_qemu_ld16s,
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#if TCG_TARGET_REG_BITS == 32
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[MO_UL] = INDEX_op_qemu_ld32,
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[MO_SL] = INDEX_op_qemu_ld32,
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#else
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[MO_UL] = INDEX_op_qemu_ld32u,
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[MO_SL] = INDEX_op_qemu_ld32s,
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#endif
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[MO_Q] = INDEX_op_qemu_ld64,
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};
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static const TCGOpcode old_st_opc[4] = {
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[MO_UB] = INDEX_op_qemu_st8,
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[MO_UW] = INDEX_op_qemu_st16,
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[MO_UL] = INDEX_op_qemu_st32,
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[MO_Q] = INDEX_op_qemu_st64,
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};
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void tcg_gen_qemu_ld_i32(TCGv_i32 val, TCGv addr, TCGArg idx, TCGMemOp memop)
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{
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memop = tcg_canonicalize_memop(memop, 0, 0);
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if (TCG_TARGET_HAS_new_ldst) {
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*tcg_ctx.gen_opc_ptr++ = INDEX_op_qemu_ld_i32;
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tcg_add_param_i32(val);
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tcg_add_param_tl(addr);
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*tcg_ctx.gen_opparam_ptr++ = memop;
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*tcg_ctx.gen_opparam_ptr++ = idx;
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return;
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}
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/* The old opcodes only support target-endian memory operations. */
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assert((memop & MO_BSWAP) == MO_TE || (memop & MO_SIZE) == MO_8);
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assert(old_ld_opc[memop & MO_SSIZE] != 0);
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if (TCG_TARGET_REG_BITS == 32) {
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*tcg_ctx.gen_opc_ptr++ = old_ld_opc[memop & MO_SSIZE];
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tcg_add_param_i32(val);
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tcg_add_param_tl(addr);
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*tcg_ctx.gen_opparam_ptr++ = idx;
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} else {
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TCGv_i64 val64 = tcg_temp_new_i64();
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*tcg_ctx.gen_opc_ptr++ = old_ld_opc[memop & MO_SSIZE];
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tcg_add_param_i64(val64);
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tcg_add_param_tl(addr);
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*tcg_ctx.gen_opparam_ptr++ = idx;
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tcg_gen_trunc_i64_i32(val, val64);
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tcg_temp_free_i64(val64);
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}
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}
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void tcg_gen_qemu_st_i32(TCGv_i32 val, TCGv addr, TCGArg idx, TCGMemOp memop)
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{
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memop = tcg_canonicalize_memop(memop, 0, 1);
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if (TCG_TARGET_HAS_new_ldst) {
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*tcg_ctx.gen_opc_ptr++ = INDEX_op_qemu_st_i32;
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tcg_add_param_i32(val);
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tcg_add_param_tl(addr);
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*tcg_ctx.gen_opparam_ptr++ = memop;
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*tcg_ctx.gen_opparam_ptr++ = idx;
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return;
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}
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/* The old opcodes only support target-endian memory operations. */
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assert((memop & MO_BSWAP) == MO_TE || (memop & MO_SIZE) == MO_8);
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assert(old_st_opc[memop & MO_SIZE] != 0);
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if (TCG_TARGET_REG_BITS == 32) {
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*tcg_ctx.gen_opc_ptr++ = old_st_opc[memop & MO_SIZE];
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tcg_add_param_i32(val);
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tcg_add_param_tl(addr);
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*tcg_ctx.gen_opparam_ptr++ = idx;
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} else {
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TCGv_i64 val64 = tcg_temp_new_i64();
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tcg_gen_extu_i32_i64(val64, val);
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*tcg_ctx.gen_opc_ptr++ = old_st_opc[memop & MO_SIZE];
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tcg_add_param_i64(val64);
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tcg_add_param_tl(addr);
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*tcg_ctx.gen_opparam_ptr++ = idx;
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tcg_temp_free_i64(val64);
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}
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}
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void tcg_gen_qemu_ld_i64(TCGv_i64 val, TCGv addr, TCGArg idx, TCGMemOp memop)
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{
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memop = tcg_canonicalize_memop(memop, 1, 0);
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#if TCG_TARGET_REG_BITS == 32
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if ((memop & MO_SIZE) < MO_64) {
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tcg_gen_qemu_ld_i32(TCGV_LOW(val), addr, idx, memop);
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if (memop & MO_SIGN) {
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tcg_gen_sari_i32(TCGV_HIGH(val), TCGV_LOW(val), 31);
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} else {
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tcg_gen_movi_i32(TCGV_HIGH(val), 0);
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}
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return;
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}
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#endif
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if (TCG_TARGET_HAS_new_ldst) {
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*tcg_ctx.gen_opc_ptr++ = INDEX_op_qemu_ld_i64;
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tcg_add_param_i64(val);
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tcg_add_param_tl(addr);
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*tcg_ctx.gen_opparam_ptr++ = memop;
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*tcg_ctx.gen_opparam_ptr++ = idx;
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return;
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}
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/* The old opcodes only support target-endian memory operations. */
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assert((memop & MO_BSWAP) == MO_TE || (memop & MO_SIZE) == MO_8);
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assert(old_ld_opc[memop & MO_SSIZE] != 0);
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*tcg_ctx.gen_opc_ptr++ = old_ld_opc[memop & MO_SSIZE];
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tcg_add_param_i64(val);
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tcg_add_param_tl(addr);
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*tcg_ctx.gen_opparam_ptr++ = idx;
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}
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void tcg_gen_qemu_st_i64(TCGv_i64 val, TCGv addr, TCGArg idx, TCGMemOp memop)
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{
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memop = tcg_canonicalize_memop(memop, 1, 1);
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#if TCG_TARGET_REG_BITS == 32
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if ((memop & MO_SIZE) < MO_64) {
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tcg_gen_qemu_st_i32(TCGV_LOW(val), addr, idx, memop);
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return;
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}
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#endif
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if (TCG_TARGET_HAS_new_ldst) {
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*tcg_ctx.gen_opc_ptr++ = INDEX_op_qemu_st_i64;
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tcg_add_param_i64(val);
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tcg_add_param_tl(addr);
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*tcg_ctx.gen_opparam_ptr++ = memop;
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*tcg_ctx.gen_opparam_ptr++ = idx;
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return;
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}
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/* The old opcodes only support target-endian memory operations. */
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assert((memop & MO_BSWAP) == MO_TE || (memop & MO_SIZE) == MO_8);
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assert(old_st_opc[memop & MO_SIZE] != 0);
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*tcg_ctx.gen_opc_ptr++ = old_st_opc[memop & MO_SIZE];
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tcg_add_param_i64(val);
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tcg_add_param_tl(addr);
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*tcg_ctx.gen_opparam_ptr++ = idx;
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}
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static void tcg_reg_alloc_start(TCGContext *s)
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{
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@ -893,6 +1075,22 @@ static const char * const cond_name[] =
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[TCG_COND_GTU] = "gtu"
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};
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static const char * const ldst_name[] =
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{
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[MO_UB] = "ub",
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[MO_SB] = "sb",
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[MO_LEUW] = "leuw",
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[MO_LESW] = "lesw",
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[MO_LEUL] = "leul",
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[MO_LESL] = "lesl",
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[MO_LEQ] = "leq",
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[MO_BEUW] = "beuw",
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[MO_BESW] = "besw",
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[MO_BEUL] = "beul",
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[MO_BESL] = "besl",
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[MO_BEQ] = "beq",
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};
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void tcg_dump_ops(TCGContext *s)
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{
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const uint16_t *opc_ptr;
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@ -1021,6 +1219,17 @@ void tcg_dump_ops(TCGContext *s)
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}
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i = 1;
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break;
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case INDEX_op_qemu_ld_i32:
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case INDEX_op_qemu_st_i32:
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case INDEX_op_qemu_ld_i64:
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case INDEX_op_qemu_st_i64:
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if (args[k] < ARRAY_SIZE(ldst_name) && ldst_name[args[k]]) {
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qemu_log(",%s", ldst_name[args[k++]]);
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} else {
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qemu_log(",$0x%" TCG_PRIlx, args[k++]);
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}
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i = 1;
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break;
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default:
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i = 0;
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break;
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