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disas/riscv: Add support for XVentanaCondOps

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This patch adds XVentanaCondOps support to the RISC-V disassembler.

Co-developed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-Id: <20230612111034.3955227-8-christoph.muellner@vrull.eu>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Christoph Müllner 2023-06-12 13:10:33 +02:00 • committed by Alistair Francis
parent c859a2424d
commit f6f72338d8
4 changed files with 67 additions and 1 deletions
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18
disas/riscv-xventana.h Normal file
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/*
* QEMU disassembler -- RISC-V specific header (xventana*).
*
* Copyright (c) 2023 VRULL GmbH
*
* SPDX-License-Identifier: GPL-2.0-or-later
*/
#ifndef DISAS_RISCV_XVENTANA_H
#define DISAS_RISCV_XVENTANA_H
#include "disas/riscv.h"
extern const rv_opcode_data ventana_opcode_data[];
void decode_xventanacondops(rv_decode*, rv_isa);
#endif /* DISAS_RISCV_XVENTANA_H */