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hw/char/stm32f2xx_usart: fix TXE/TC bit handling

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I/O currently being synchronous, there is no reason to ever clear the
SR_TXE bit. However the SR_TC bit may be cleared by software writing
to the SR register, so set it on each write.

In addition, fix the reset value of the USART status register.

Signed-off-by: Richard Braun <rbraun@sceen.net>
Reviewed-by: Alistair Francis <alistair.francis@xilinx.com>
[PMM: removed XXX tag from comment, since it isn't something
 we need to come back and fix in QEMU]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Richard Braun 2018-02-22 15:12:51 +00:00 • committed by Peter Maydell
parent 1c3db49d39
commit f6bfe45af2
2 changed files with 14 additions and 5 deletions
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7
include/hw/char/stm32f2xx_usart.h
View file

@ -37,7 +37,12 @@
#define USART_CR3 0x14
#define USART_GTPR 0x18
#define USART_SR_RESET 0x00C00000
/*
* NB: The reset value mentioned in "24.6.1 Status register" seems bogus.
* Looking at "Table 98 USART register map and reset values", it seems it
* should be 0xc0, and that's how real hardware behaves.
*/
#define USART_SR_RESET (USART_SR_TXE | USART_SR_TC)
#define USART_SR_TXE (1 << 7)
#define USART_SR_TC (1 << 6)