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target/arm: Handle FPCR.AH in SVE FMLSL (indexed)
Handle FPCR.AH's requirement to not negate the sign of a NaN in SVE FMLSL (indexed), using the usual trick of negating by XOR when AH=0 and by muladd flags when AH=1. Since we have the CPUARMState* in the helper anyway, we can look directly at env->vfp.fpcr and don't need toa pass in the FPCR.AH value via the SIMD data word. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20250129013857.135256-32-richard.henderson@linaro.org [PMM: commit message tweaked] Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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1 changed files with 12 additions and 3 deletions
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@ -2250,23 +2250,32 @@ void HELPER(sve2_fmlal_zzxw_s)(void *vd, void *vn, void *vm, void *va,
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CPUARMState *env, uint32_t desc)
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{
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intptr_t i, j, oprsz = simd_oprsz(desc);
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uint16_t negn = extract32(desc, SIMD_DATA_SHIFT, 1) << 15;
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bool is_s = extract32(desc, SIMD_DATA_SHIFT, 1);
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intptr_t sel = extract32(desc, SIMD_DATA_SHIFT + 1, 1) * sizeof(float16);
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intptr_t idx = extract32(desc, SIMD_DATA_SHIFT + 2, 3) * sizeof(float16);
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float_status *status = &env->vfp.fp_status_a64;
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bool fz16 = get_flush_inputs_to_zero(&env->vfp.fp_status_f16_a64);
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int negx = 0, negf = 0;
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if (is_s) {
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if (env->vfp.fpcr & FPCR_AH) {
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negf = float_muladd_negate_product;
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} else {
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negx = 0x8000;
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}
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}
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for (i = 0; i < oprsz; i += 16) {
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float16 mm_16 = *(float16 *)(vm + i + idx);
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float32 mm = float16_to_float32_by_bits(mm_16, fz16);
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for (j = 0; j < 16; j += sizeof(float32)) {
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float16 nn_16 = *(float16 *)(vn + H1_2(i + j + sel)) ^ negn;
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float16 nn_16 = *(float16 *)(vn + H1_2(i + j + sel)) ^ negx;
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float32 nn = float16_to_float32_by_bits(nn_16, fz16);
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float32 aa = *(float32 *)(va + H1_4(i + j));
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*(float32 *)(vd + H1_4(i + j)) =
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float32_muladd(nn, mm, aa, 0, status);
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float32_muladd(nn, mm, aa, negf, status);
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}
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}
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}
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